Re: K7 performance problem on the SiS730 understood.

[Ronald G Minnich]

On Wed, 6 Jun 2001, Ollie Lho wrote:
> This seems to be "implied" by the AMD Porcessor Recognition App Note.
> It says only K7 CPUs of Model 1 and 2 need to init L2 cache.
> Model 1,2 are slot Athlon. Socket Atholon is Model 4 and Duron is
> Model 3.

I read that note too. I just didn't believe them.

oh well.

ron