On Monday 29 May 2006 20:26, Stefan Reinauer wrote:
> * Juergen Beisert <[EMAIL PROTECTED]> [060529 18:37]:
> > With write enabled E and F segments this message changes to:
> > ....
> > Devices initialized
> > Copying IRQ routing tables to 0xf0000...done.
> > Verifing copy of IRQ routing tables at 0xf0000...done
> > Checking IRQ routing table consistency...
> > check_pirq_routing_table() - irq_routing_table located at: 0x000f0000
> > done.
>
> Can you provide a patch?
Yes, attached. But I'm not sure if this is the right place to patch. Maybe
there is a better place to enable this feature?
> > But it still hangs after downloading the Linux kernel :-(
>
> Have you enabled serial console in your kernel config?
> and did you specify it on the kernel command line? (ie.
> console=ttyS0,115200n8)
Yes I did. Its not my first embedded target that I bring up (but my first with
LinuxBios). So that was the first I care for.
The UART address seems ok, so I think Linux can find and use this device.
Regards
Juergen
--- LinuxBIOSv2-2009/src/northbridge/amd/gx1/northbridge.c 2005-08-17 06:48:30.000000000 +0200
+++ LinuxBIOSv2-2009-my/src/northbridge/amd/gx1/northbridge.c 2006-05-30 11:01:32.000000000 +0200
@@ -24,9 +24,17 @@
pci_write_config8(dev, 0x44, 0x00);
}
+/**
+ * Enables memory from 0xC0000 up to 0xFFFFF.
+ * So this region is read/write and cache able
+ *
+ * FIXME: What about PCI master access into
+ * this region?
+ **/
static void enable_shadow(device_t dev)
{
-
+ writel(0x77777777,GX_BASE+BC_XMAP_2);
+ writel(0x77777777,GX_BASE+BC_XMAP_3);
}
static void northbridge_init(device_t dev)
--
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