Can you check the SERR and PERR status in the bridge before the enable? (they are in offset 1f of config space) If you clear them first, does it help? We have a platform with a different southbridge where we find that to be the case (clearing the status bits first makes it not hang)
On 9/13/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > Quoting Peter Stuge <[EMAIL PROTECTED]>: > > > On Thu, Sep 13, 2007 at 02:40:16AM -0400, [EMAIL PROTECTED] wrote: > >> I wonder if my nic needs the pci rom to get it going, and this > >> would solve the problem? > > > > The ROM would be used much later in the init process, so no, it's not > > likely to help. :\ > > > > > After a few tests I found the problem. It is locking up on this line: > > pci_write_config16(dev, PCI_COMMAND, command); > > It is trying to write to the CMD(0x04) register of the PCI Bridge. > Looks like it is trying to write 0x0141. Setting the SERR# Enable > (SERR_EN), Parity Error Response (PER), and I/O Space Enable (IOSE). > > I have no idea why this would cause a lock up??? I doesn't on any of > the other devices?? Could someone take a look at the i82801DB > datasheet and tell me if I am missing something?? Sometimes two (or > more) heads are better than one. > > > Thanks - Joe > > -- > linuxbios mailing list > linuxbios@linuxbios.org > http://www.linuxbios.org/mailman/listinfo/linuxbios > -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
