[Sorry for being late, I'm a bit, um... Internet-challenged at the moment.
No PGP signature for the same reason.]
On Wed, Sep 26, 2007 at 11:50:52AM +0200, Robert Millan wrote:
> On Tue, Sep 25, 2007 at 03:53:21PM -0700, ron minnich wrote:
> > Robert, I understand the reason for the include of the .c files, but
> > go ahead and just copy the code. We've tried both ways, over the
> > years, and it's better to clone the code, since the vendors have a
> > habit of changing things on mainboards, and code that includes other
> > code can cause trouble in both directions.
I strongly disagree with this approach. Duplicated code is bad, bad,
bad and should be avoided whereever possible.
Now, in order to not only complain, here's a demo patch which completely
avoids copying a single file. One code base for the
- ASUS A8N-E
- ASUS A8N5X
- ASUS A8NE-FM/S (I'll send an extra patch for that later)
No duplicated code whatsoever. Sure, this may not be too elegant
(there's some room for improvements, though), but it's definately a
_lot_ better than duplicating all those files.
This is (manually) build-tested for the A8N-E and A8N5X and worked for me.
I did not test the produced ROMs, though.
In addition to the patch, you need to create a symlink
src/mainboard/asus/a8n_e -> src/mainboard/asus/a8n5x
in order to make the build system happy.
Uwe.
Add support for the ASUS A8N5X by special-casing it in the A8N-E code.
Signed-off-by: Robert Millan <[EMAIL PROTECTED]>
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Index: src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- src/mainboard/asus/a8n_e/Config.lb (Revision 2811)
+++ src/mainboard/asus/a8n_e/Config.lb (Arbeitskopie)
@@ -226,6 +226,8 @@
config chip.h
end
+if CONFIG_BOARD_A8N_E
+
chip northbridge/amd/amdk8/root_complex # Root complex
device apic_cluster 0 on # APIC cluster
chip cpu/amd/socket_939 # Socket 939 CPU
@@ -346,3 +348,103 @@
end
end
end
+
+end # if
+
+if CONFIG_BOARD_A8N5X
+
+chip northbridge/amd/amdk8/root_complex # Root complex
+ device apic_cluster 0 on # APIC cluster
+ chip cpu/amd/socket_939 # Socket 939 CPU
+ device apic 0 on end # APIC
+ end
+ end
+
+ device pci_domain 0 on # PCI domain
+ chip northbridge/amd/amdk8 # mc0
+ device pci 18.0 on # Northbridge
+ # Devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804 # Southbridge
+ device pci 0.0 on end # HT
+ device pci 1.0 on # LPC
+ chip superio/ite/it8712f # Super I/O
+ device pnp 2e.7 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.8 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.9 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.a on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x71 = 2
+ end
+ device pnp 2e.b off end # Midi port
+ device pnp 2e.c off end # Game port
+ end
+ end
+ device pci 1.1 on # SM 0
+ # chip drivers/generic/generic #dimm 0-0-0
+ # device i2c 50 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-0-1
+ # device i2c 51 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-1-0
+ # device i2c 52 on end
+ # end
+ # chip drivers/generic/generic #dimm 0-1-1
+ # device i2c 53 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-0-0
+ # device i2c 54 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-0-1
+ # device i2c 55 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-1-0
+ # device i2c 56 on end
+ # end
+ # chip drivers/generic/generic #dimm 1-1-1
+ # device i2c 57 on end
+ # end
+ end
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 off end # Onboard audio (ACI)
+ device pci 4.1 off end # Onboard modem (MCI)
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on end # PCI
+ device pci a.0 on end # NIC
+ device pci b.0 on end # PCI E 3
+ device pci c.0 on end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
+ # register "mac_eeprom_smbus" = "3"
+ # register "mac_eeprom_addr" = "0x51"
+ end
+ end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ end
+end
+
+end # if
+
Index: src/mainboard/asus/a8n_e/Options.lb
===================================================================
--- src/mainboard/asus/a8n_e/Options.lb (Revision 2811)
+++ src/mainboard/asus/a8n_e/Options.lb (Arbeitskopie)
@@ -102,7 +102,13 @@
uses CONFIG_LB_MEM_TOPK
+uses CONFIG_BOARD_A8N_E
+uses CONFIG_BOARD_A8N5X
+default CONFIG_BOARD_A8N_E = 0
+default CONFIG_BOARD_A8N5X = 0
+
+
## ROM_SIZE is the size of boot ROM that this board will use.
## ---> 512 Kbytes
default ROM_SIZE=(512*1024)
Index: src/config/Options.lb
===================================================================
--- src/config/Options.lb (Revision 2811)
+++ src/config/Options.lb (Arbeitskopie)
@@ -168,6 +168,17 @@
comment "Use stage 1 initialization code"
end
+define CONFIG_BOARD_A8N_E
+ default 0
+ export used
+ comment "TODO"
+end
+define CONFIG_BOARD_A8N5X
+ default 0
+ export used
+ comment "TODO"
+end
+
###############################################
# ROM image options
###############################################
Index: targets/asus/a8n5x/Config.lb
===================================================================
--- targets/asus/a8n5x/Config.lb (Revision 0)
+++ targets/asus/a8n5x/Config.lb (Revision 0)
@@ -0,0 +1,56 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Philipp Degler <[EMAIL PROTECTED]>
+## (Thanks to LSRA University of Mannheim for their support)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target asus_a8n5x
+mainboard asus/a8n5x
+
+option CONFIG_BOARD_A8N5X = 1
+
+romimage "normal"
+ option USE_FAILOVER_IMAGE=0
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x20000
+ option XIP_ROM_SIZE=0x20000
+ option LINUXBIOS_EXTRA_VERSION="_Normal"
+# payload ../../../../../../payloads/dummy.elf
+ payload ../../../../../../payloads/filo.elf
+end
+
+romimage "fallback"
+ option USE_FAILOVER_IMAGE=0
+ option USE_FALLBACK_IMAGE=1
+ option ROM_IMAGE_SIZE=0x20000
+ option XIP_ROM_SIZE=0x20000
+ option LINUXBIOS_EXTRA_VERSION="_Fallback"
+# payload ../../../../../../payloads/memtest.elf
+ payload ../../../../../../payloads/filo.elf
+end
+
+romimage "failover"
+ option USE_FAILOVER_IMAGE=1
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=FAILOVER_SIZE
+ option XIP_ROM_SIZE=FAILOVER_SIZE
+ option LINUXBIOS_EXTRA_VERSION="_Failover"
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
Index: targets/asus/a8n_e/Config.lb
===================================================================
--- targets/asus/a8n_e/Config.lb (Revision 2811)
+++ targets/asus/a8n_e/Config.lb (Arbeitskopie)
@@ -22,6 +22,8 @@
target asus_a8n_e
mainboard asus/a8n_e
+option CONFIG_BOARD_A8N_E = 1
+
romimage "normal"
option USE_FAILOVER_IMAGE=0
option USE_FALLBACK_IMAGE=0
--
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