Add post codes so that we have a better idea where it fails, if it fails. ron
Add some post codes so we have some idea where it fails. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: arch/x86/geodelx/stage0.S =================================================================== --- arch/x86/geodelx/stage0.S (revision 518) +++ arch/x86/geodelx/stage0.S (working copy) @@ -183,6 +183,7 @@ movw %ax, %fs movw %ax, %gs + port80_post(0x02) /* Restore the BIST value to %eax. */ movl %ebp, %eax @@ -193,6 +194,7 @@ /* DCacheSetup: Setup data cache for use as RAM for a stack. */ DCacheSetup: invd + port80_post(0x03) /* Set cache properties. */ movl $CPU_RCONF_DEFAULT, %ecx @@ -207,12 +209,14 @@ */ movl $CPU_DM_CONFIG0,%ecx rdmsr + port80_post(0x04) /* TODO: Make consistent with i$ init, either whole reg = 0, or just * this bit... */ andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax wrmsr + port80_post(0x05) /* Get cache timing params from BIOS config data locations and apply. */ /* Fix delay controls for DM and IM arrays. */ @@ -220,27 +224,32 @@ xorl %edx, %edx movl $0x2814D352, %eax wrmsr + port80_post(0x06) movl $CPU_BC_MSS_ARRAY_CTL1, %ecx xorl %edx, %edx movl $0x1068334D, %eax wrmsr + port80_post(0x07) movl $CPU_BC_MSS_ARRAY_CTL2, %ecx movl $0x00000106, %edx movl $0x83104104, %eax wrmsr + port80_post(0x08) movl $GLCP_FIFOCTL, %ecx rdmsr movl $0x00000005, %edx wrmsr + port80_post(0x09) /* Enable setting. */ movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx xorl %edx, %edx movl $0x01, %eax wrmsr + port80_post(0x0a) /* Get cleaned up. */ xorl %edi, %edi @@ -257,6 +266,7 @@ xorl %eax, %eax movl $CPU_DC_INDEX, %ecx wrmsr + port80_post(0x0b) /* Start address for tag of Way0: ebp will hold the incrementing * address. Don't destroy! @@ -272,6 +282,7 @@ * the line counter. Don't destroy! */ movl $LX_NUM_CACHELINES, %edi + port80_post(0x0c) DCacheSetupFillWay: /* Fill with dummy data: zero it so we can tell it from PCI memory @@ -287,6 +298,7 @@ wrmsr decw %si jnz DCacheSetup_quadWordLoop + port80_post(0x0d) /* Set the tag for this line, need to do this for every new cache * line to validate it! @@ -298,6 +310,7 @@ movl %ebp, %eax movl $CPU_DC_TAG, %ecx wrmsr + port80_post(0x0e) /* Switch to next line. Lines are in bits 10:4. */ /* When index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is @@ -311,6 +324,7 @@ */ addl $0x010, %eax wrmsr + port80_post(0x0f) decl %edi jnz DCacheSetupFillWay @@ -331,6 +345,7 @@ /* Let's be sure: reset line index bits 10:4. */ andl $0xFFFFF80F, %eax wrmsr + port80_post(0x11) jmp DCacheSetupFillWay @@ -364,6 +379,7 @@ outb %al, $0x80 DCacheSetupBad: + port80_post(0xFF) hlt /* Issues */ jmp DCacheSetupBad
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