Ronald G Minnich <[EMAIL PROTECTED]> writes:
> I need to know how to turn on 266 FSB in linuxbios then. Our performance
> right now on this board is not good due to K7 cache, I think, but once we
> get K7 L2 up then it would also be nice to turn on 266 FSB.
>
>
> AMD keeps insisting I don't need to turn it l2 on, "it's already on"? why
> then does my memory speed report at 3.4 microseconds.
>
> Can someone just DESCRIBE what you do to turn L2 on?
>
> Then we need a "266 FSB" HOWTO.
Ollie to complete this story, I help Ron perform an experiment to
see if the L2 cache was enbabled. And it turned out very badly. With
results indicating that caching was simply disabled, or worse.
The attached program attempts to measure memory access times, to see how
fast L1, L2, and memory are. Unless hand tuned in assembly it gets the times
wrong. However it comes close enough that you can see the speed differences
in the various caches, and pretty much tell how large they are.
The attached program interates in a loop doing memory reads and writes
from an array, until at least one second has passed. Then it repeats
the loop without touching memory and subtracts off the time of the
second loop. This loop takes several minutes instead of seconds to
run on Ron's SIS Athlon board running linuxBIOS.
Something is very wrong. Ollie if you could offer an opinion it would
be great.
If someone else besides Ron could reproduce this it would help. I'm
hoping to have a different chipset board to test this up on in a few
weeks, but I'm currently in the fun limbo where I don't yet have
debugging output to the serial port :)
Eric
#include <stdio.h>
#include <sys/times.h>
#include <sys/types.h>
#include <time.h>
#define CACHE_MIN (1) /* smallest cache */
#define CACHE_MAX (2048*1024) /* largest cache */
#define SAMPLE 10 /* to get a larger time sample */
#ifndef CLK_TCK
#define CLK_TCK 60.0 /* number oclock ticks per second */
#endif
volatile int x[CACHE_MAX];
double get_seconds(void) /* routine to read time */
{
struct tms rusage;
double result;
times(&rusage);
result = (double)(rusage.tms_utime)/ CLK_TCK;
return result;
}
#define REPS (SAMPLE*CACHE_MAX)
int main(int argc, char **argv)
{
int /* register */ i, index, stride;
int register /* volatile */ temp;
int /* register */ steps, tsteps, csize, i_start;
double register sec0, sec; /*timing variuables */
int csize_min, csize_max;
csize_min = CACHE_MIN;
csize_max = CACHE_MAX;
if (argc > 1) {
csize_min = atoi(argv[1])/sizeof(int);
}
if (argc > 2) {
csize_max = atoi(argv[2])/sizeof(int);
}
if (csize_min < CACHE_MIN) {
csize_min = CACHE_MIN;
}
if (csize_max > CACHE_MAX) {
csize_max = CACHE_MAX;
}
for(csize = csize_min; csize <= csize_max; csize = csize *2)
for( stride = 1; stride <= csize; stride = stride *2) {
sec = 0.0;
i_start = SAMPLE*stride*(CACHE_MAX/csize);
steps = 0;
do {
sec0 = get_seconds();
for (i = i_start; i != 0; i= i-1)
for (index = 0; index < csize; index = index
+stride)
x[index] = x[index]+76;
steps = steps +1;
sec = sec + (get_seconds() - sec0);
} while (sec < 1.0);
tsteps = steps;
steps = 0;
do {
sec0 = get_seconds();
for (i = i_start; i != 0; i= i-1)
for (index = 0; index < csize; index = index
+stride)
temp = temp + 76;
steps = steps +1;
sec = sec - (get_seconds() - sec0);
} while (steps < tsteps);
printf("Size: %7d Stride: %7d read+write:%14.10f ns\n",
csize *sizeof(int),
stride * sizeof(int),
(sec *1e9) / ((double)(REPS*steps)));
fflush(stdout);
};
return 0;
}
