I've been working on reading all of the appropriate values
from SPD on the Dual Athlon board.
I'm almost done. I have code to set the all of the interesting timing
registers especially CAS latency to their optimal value legal value
with SPD written, and tested.
I currently have 3 more kinds of information to read from SPD but they
are trivial. After I get some sleep I'll finish them off.
The only interesting thing I have left off is zeroing ECC SDRAM,
and making certain if I have 4GB of ram installed I have some address
space left over for hardware devices.
So I'm just a touch behind of my goal of friday to start committing
but not by much. Anyway in the next couple of days I'll have the
full ram initialization behind me, and I can fix the rest of the bugs.
Right now I'm going to go to bed and go to sleep though.
Eric
