On 24 Sep 2001, Eric W. Biederman wrote:
>
> I just skimmed a review of the Nvidia nForce chipset. Wondering
> why the memory bandwidth did not noticeably increase when dual-channel
> DDR SDRAM was added I looked at the athlon system bus. It turns
> out that an athlon uses a 72 pin data bus running at 133Mhz. Exactly as
> DDR SDRAM does. So the maximum processor bandwidth of the Athlon is only
> better than the maximum bandwidth of DDR SDRAM because it has a seperate
> 13 bit command channel.
So the big deal is the "double pump", i.e. clocking data on each edge,
right? That gets to 16 bytes (I'm assuming it's an ECC bus) * 266 Mhz if
my math is right which means ~4 Gbytes/second. Ok, but not great.
Wonder what the next trick will be? It's hard to image doubling the width
...
ron
