Ollie Lho <[EMAIL PROTECTED]> writes: > Eric W. Biederman wrote: > > > There are a lot of files using this trick, for examples, > rom/*_fill_infub.c. Are we going to convert all these files ??
Probably. Since the configuration system isn't the core focus I have a pretty opportunistic attitude towards this stuff. When I trip over it I'll fix it. But it can probably help to reduce our build times. > > The solutions is still a little incomplete because I don't have > > rules for setting one variable from another in the Config language > > yet. But otherwise it works out fairly well. > > > > > Something like > > option NEED_FOLLOWING_MACROS MACRO1 (boolean op ??) MACRO2 Right. > Or why don't you just put some conditional construct in if it > is really neceressary ? That is the plan. To attack this when it is really necessary. I've come pretty close lately to needing something. But again I'm opportunistic. I fix it when it gets in the way. > P.S. The current K7 cpufixup really sucks. It does not work on my MB > :-(. Ouch. I'm not really suprised. But the technique is good enough that someone who isn't encumbered by having an NDA to the magic formula should be able to work it out. Heck you can get 90% of it by seeing which registers very with memory size. And the code for enabling SSE has shown up on the linux kernel mailing list. Though right now I'm not to keen on the Athlon because I can't do my cache as ram trick. I love doing my memory setup in C. The Intel engineers almost have something to talk about when they talk about how complex DDR SDRAM is to setup. RDRAM has more registers and more chips, but the intel chipssets don't really support any variety of chips. The 860 chipset only supports 32MB or 16MB chips, within a very narrow variation range, in timings. I keep wondering what it would take to port the cache as ram trick to the P6 core in. There is certainly room in the cache but to port to CPUs earlier than the PIII it would require the L2 cache enable code to be in assemly which is almost as nasty as the memory turn on. The L2 cache is unified for both instructions and data (and is > 16KB) so it looks to the the only cache level worth messing with. As the P6 family is not dead yet it is worth looking into. Eric
