Eric W. Biederman wrote:
>
> Though right now I'm not to keen on the Athlon because I can't
> do my cache as ram trick. I love doing my memory setup in C.
>
> The Intel engineers almost have something to talk about when they talk
> about how complex DDR SDRAM is to setup. RDRAM has more registers
> and more chips, but the intel chipssets don't really support any
> variety of chips. The 860 chipset only supports 32MB or 16MB chips,
> within a very narrow variation range, in timings.
>
> I keep wondering what it would take to port the cache as ram
> trick to the P6 core in. There is certainly room in the cache
> but to port to CPUs earlier than the PIII it would require
> the L2 cache enable code to be in assemly which is almost as
> nasty as the memory turn on. The L2 cache is unified for both
> instructions and data (and is > 16KB) so it looks to the the only
> cache level worth messing with. As the P6 family is not dead
> yet it is worth looking into.
>
I still don't get it as why/how yo are doing this:
1. If you only what to do raminit in C, the only thing you
need is stack, isn't L1 (data) cache enough for you ??
2. If you are treating code as data and jump to code in the
cache (e.g for IPL + SPL cases) you need unified cache.
But can you just enable L2 but not L1 ?? How does L1
affect the whole procedure ??
Ollie
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