nope. It's broken.
This is L440GX+, SMP. Things go badly once the second CPU starts to come up ... Setting up local apic...done. CPU #1 Initialized BOOT CPU is 1 Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +start_eip=0x00090000 #startup loops: 2. Sending STARTUP #1 to 0. After apic_write. etartupc ppoiunt_ 1r. fsaietitng 0 or seandp tio cfi:ni sh..0. TU0S0end0in0g 0ST0AR m P #c2 ptou 0 . Aeftmero arpiyc_ wrsitie.z poStsaretutp int 1. Waiting for send to finish... +After Startup. Allocating PCI resources...COMPUTE_ALLOCATE: do IO compute_allocate_io: base 0x1000 compute_allocate_io: base 0x1000 compute_allocate_io: base 0x1000 BUS 2: set iolimit to 0xfff BUSIO: done Bridge Bus 0x2, iobase now 0x1000 Note all the garbage. And it seems like the second PCU decides to start beating on the PCI bus to allocate resources, bad bad bad. ron
