Following up to myself again...
> There are quite a few Geode boards available. Some examples:
>
> The Voyagers from www.cocom.co.uk (i think that they have a SC1200
> board too but I don't know if it's available for buying)
I went through my wardwobe and finally found my Cocom Voyager 2. So,
for your enjoyment, here's a patch that splits up the NatSemi SCx200
support into generic GX1 stuff that can be reused for a GX1/CS5530
combo and for a SCx200 system. There are a lot of new files in the
nortbridge and southbridge directories and the nortshouthbridge/NSC
directory should be deleted. I've fixed a few bugs on the way too.
This code seems to work both on the Cocom Voyager 2 and on an Ericsson
NanoCube and gets as far as wanting to load the kernel. I haven't
figured out how the DiskOnChip loader works yet, so I haven't actually
loaded a kernel on these systems, but it ought to work.
There is also some new code for a NatSemi PC97317 SuperIO that can be
found on both boards I have. I don't think this will help those of
you who have a Lippert board since if I understood correctly, it
uses a different SuperIO. But as soon as you can get a serial port
working, the rest of the code ought to work. *knock on wood*
/Christer (they're coming to take me away, haha,
I think I ought to get some sleep :-)
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/cocom/voyager2/Config
freebios/src/mainboard/cocom/voyager2/Config
--- freebios.orig/src/mainboard/cocom/voyager2/Config Thu Jan 1 01:00:00 1970
+++ freebios/src/mainboard/cocom/voyager2/Config Fri Mar 15 09:23:28 2002
@@ -0,0 +1,82 @@
+# Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+# This is a config file for the Cocom Voyager 2 board
+# <URL:http://www.cocom.co.uk>
+
+# The Voyager 2 is a National Semiconductor GX1 + CS5530 + PC93917
+# design. It is a fairly complete PC with VGA, one serial port, one
+# IrDA header, one parallel port, two USB ports, a PS/2 Keyboard
+# connector (can also be used for a PS/2 Mouse using a splitter
+# cable), floppy, IDE and finally one ethernet port using a RTL8139
+# ethernet chip. Other than that the board has a DiskOnChip socket
+# and a PC104 connector for expansion.
+
+arch i386
+cpu p5
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript cpu/i386/entry16.lds
+ldscript cpu/i386/entry32.lds
+mainboardinit cpu/i386/reset16.inc
+ldscript cpu/i386/reset16.lds
+
+########################################################################
+
+mainboardinit superio/NSC/pc97317/sio_setup.inc
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+
+########################################################################
+
+northbridge nsc/gx1
+southbridge nsc/cs5530
+superio NSC/pc97317
+
+########################################################################
+# Lots of constans, you probably don't need to change anything here.
+
+# GX_BASE is the address of a configuration memory region for the GX1
+# processor. You probably don't want to change this.
+option GX_BASE=0x40000000
+
+########################################################################
+# Super I/O configuration
+
+# The SIO is pin strapped to show up at address 0x2e
+option SIO_BASE=0x2e
+
+# Serial Port 1
+option SIO_SP1_BASE=0x3f8
+option SIO_SP1_IRQ=4
+
+# Serial Port 2 is connected to an IrDA header
+#option SIO_SP2_BASE=0x2f8
+#option SIO_SP2_IRQ=3
+
+# Parallel port
+option SIO_PP_BASE=0x278
+option SIO_PP_IRQ=7
+
+# GPIO Pins
+option SIO_GPIO_BASE=0xe0
+
+########################################################################
+# Southbridge configuration
+
+option CS5530_INTA=9
+option CS5530_INTB=10
+option CS5530_INTC=11
+option CS5530_INTD=15
+
+option CS5530_PRIMARY_IDE=1
+#option CS5530_SECONDARY_IDE=1
+
+########################################################################
+
+option NO_KEYBOARD
+option FINAL_MAINBOARD_FIXUP=1
+object mainboard.o
+
+# Local variables:
+# compile-command: "make -C /export/bios/voyager2"
+# End:
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/cocom/voyager2/config.example
freebios/src/mainboard/cocom/voyager2/config.example
--- freebios.orig/src/mainboard/cocom/voyager2/config.example Thu Jan 1 01:00:00
1970
+++ freebios/src/mainboard/cocom/voyager2/config.example Fri Mar 15 09:23:28
+2002
@@ -0,0 +1,33 @@
+# Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+# This is an example configuration file for the Cocom Voyager 2
+# See src/mainboard/cocom/voyager2/Config for more information
+
+target voyager2
+mainboard cocom/voyager2
+
+# Enable Serial Console for debugging
+option SERIAL_CONSOLE=1
+option TTYS0_BAUD=38400
+
+option DEFAULT_CONSOLE_LOGLEVEL=9
+option DEBUG
+
+#option INBUF_COPY
+option RAMTEST
+#option BOOT_IDE=1
+#option BOOT_TFTP=1
+
+#option USE_ELF_BOOT=1
+option USE_GENERIC_ROM=1
+option ZKERNEL_START=0xc0000200
+option ZKERNEL_MASK=0xffff
+option ROM_SIZE=262144
+
+# Path to your kernel (vmlinux)
+linux /export/nano/linux
+
+# Kernel command line parameters
+commandline root=/dev/hda2 console=ttyS0,38400 reboot=h
+#commandline root=/dev/nfs ip=dhcp console=ttyS0,38400
+
+
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/cocom/voyager2/mainboard.c
freebios/src/mainboard/cocom/voyager2/mainboard.c
--- freebios.orig/src/mainboard/cocom/voyager2/mainboard.c Thu Jan 1 01:00:00
1970
+++ freebios/src/mainboard/cocom/voyager2/mainboard.c Fri Mar 15 09:23:28 2002
@@ -0,0 +1,48 @@
+/*
+ freebios/src/mainboard/cocom/voyager2/mainboard.c
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Mainboard fixup for the Cocom Voyager 2
+*/
+
+#include <printk.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <cpu/p5/io.h>
+
+#include <types.h>
+
+void
+mainboard_fixup()
+{
+}
+
+void
+final_mainboard_fixup()
+{
+#if 0
+ struct pci_dev *dev;
+ int i;
+#endif
+
+ void final_southbridge_fixup(void);
+ final_southbridge_fixup();
+
+ printk_info("Final mainboard fixup\n");
+
+#if 0
+ dev = pci_find_slot(0, PCI_DEVFN(0x0f, 0));
+ if (dev) {
+ printk_debug("nano: Setting eth0 IRQ to %d\n", SCx200_INTA);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, SCx200_INTA);
+ }
+#endif
+}
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ c-basic-offset: 8
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/nano/nano/Config
freebios/src/mainboard/nano/nano/Config
--- freebios.orig/src/mainboard/nano/nano/Config Fri Mar 15 08:18:38 2002
+++ freebios/src/mainboard/nano/nano/Config Fri Mar 15 09:23:41 2002
@@ -13,6 +13,7 @@
# for debugging and not really for production use.
arch i386
+cpu p5
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript cpu/i386/entry16.lds
@@ -21,6 +22,18 @@
ldscript cpu/i386/reset16.lds
########################################################################
+
+mainboardinit southbridge/nsc/scx200/scx200_setup.inc
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+
+########################################################################
+# Just about everything is integrated in the SCx200
+
+northbridge nsc/gx1
+southbridge nsc/scx200
+
+########################################################################
# Where the Disk On Chip Chip Select pin is mapped in memory.
# See the SCx200 databook for more information.
@@ -97,30 +110,11 @@
#option SCx200_SECONDARY_IDE
########################################################################
-# Finally, the code
-
-# This must be done before the serial port is initialized, so
-# it has to be here.
-mainboardinit northsouthbridge/NSC/scx200/chipset_setup.inc
-
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-
-northsouthbridge NSC/scx200
option NO_KEYBOARD
-
option FINAL_MAINBOARD_FIXUP=1
object mainboard.o
-# The PIRQ table doesn't seem to work properly, so the PCI interrupts
-# are set up in final_mainboard_fixup instead.
-# FIXME -- build a working irq table
-#option HAVE_PIRQ_TABLE=1
-#object irq_tables.o
-
-cpu p5
-
# Local variables:
-# compile-command: "make -C /export/nano/bios/nano"
+# compile-command: "make -C /export/bios/nano"
# End:
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/nano/nano/config.example
freebios/src/mainboard/nano/nano/config.example
--- freebios.orig/src/mainboard/nano/nano/config.example Fri Mar 15 08:18:38
2002
+++ freebios/src/mainboard/nano/nano/config.example Fri Mar 15 09:23:41 2002
@@ -29,6 +29,11 @@
# DOC socket that causes it to write garbage to address 0x80 of the
# flash chip.
+# For some strange reason the kernel fails to boot when I use a high ROMBASE
+#option _ROMBASE=0xffff0000
+
+#option USE_ELF_BOOT=1
+
option USE_GENERIC_ROM=1
option ZKERNEL_START=0xc0000200
option ZKERNEL_MASK=0xffff
@@ -45,7 +50,7 @@
linux /export/nano/linux
# Kernel command line parameters
-commandline root=/dev/hda2 console=ttyS0,38400
+commandline root=/dev/hda2 console=ttyS0,38400 reboot=h
#commandline root=/dev/nfs ip=dhcp console=ttyS0,38400
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/mainboard/nano/nano/mainboard.c
freebios/src/mainboard/nano/nano/mainboard.c
--- freebios.orig/src/mainboard/nano/nano/mainboard.c Fri Mar 15 08:18:38 2002
+++ freebios/src/mainboard/nano/nano/mainboard.c Fri Mar 15 09:23:41 2002
@@ -75,7 +75,7 @@
/*
Local variables:
- compile-command: "make -C /export/nano/bios/nano"
+ compile-command: "make -C /export/bios/nano"
c-basic-offset: 8
End:
*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/Config
freebios/src/northbridge/nsc/gx1/Config
--- freebios.orig/src/northbridge/nsc/gx1/Config Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/Config Fri Mar 15 09:20:52 2002
@@ -0,0 +1,12 @@
+# freebios/src/northbridge/nsc/gx1/Config
+# Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+# Configuration for the National Semiconductor GX1 processors
+
+mainboardinit northbridge/nsc/gx1/cpu_setup.inc
+mainboardinit northbridge/nsc/gx1/gx_setup.inc
+mainboardinit northbridge/nsc/gx1/northbridge_setup.inc
+
+raminit northbridge/nsc/gx1/raminit.inc
+
+object northbridge.o
+
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/cpu_setup.inc
freebios/src/northbridge/nsc/gx1/cpu_setup.inc
--- freebios.orig/src/northbridge/nsc/gx1/cpu_setup.inc Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/cpu_setup.inc Fri Mar 15 09:20:52 2002
@@ -0,0 +1,66 @@
+/*
+ freebios/src/northbridge/nsc/gx1/cpu_setup.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Initialize the GX1 CPU configuration registers
+*/
+
+cpu_setup_start:
+ leal cpu_setup_table, %esi
+ movl $cpu_setup_len, %ecx
+
+cpu_setup_loop:
+ movw (%esi), %ax
+ addl $2, %esi
+ outb %al, $0x22
+ movb %ah, %al
+ outb %al, $0x23
+ loop cpu_setup_loop
+
+ movb $0xff, %al /* DIR1 -- Identification Register 1 */
+ outb %al, $0x22
+ inb $0x23, %al
+ cmpb $0x63, %al /* Revision for GXLV rev 3 */
+ jbe cpu_no_ccr4
+
+ movb $0xe8, %al /* CCR4 */
+ outb %al, $0x22
+ inb $0x23, %al
+ orb $0x20, %al /* Enable FPU Fast Mode */
+ outb %al, $0x23
+
+ movb $0xf0, %al /* PCR1 --- Performace Control */
+ outb %al, $0x22
+ inb $0x23, %al
+ orb $0x02, %al /* Incrementor on, whatever that is */
+ outb %al, $0x23
+
+ movb $0x20, %al /* PCR0 --- Performace Control */
+ outb %al, $0x22
+ inb $0x23, %al
+ orb $0x20, %al /* Must be 1 according to data book */
+ orb $0x04, %al /* Incrementor Margin 10 */
+ outb %al, $0x23
+cpu_no_ccr4:
+
+ jmp cpu_setup_end
+
+cpu_setup_table:
+ .byte 0xc1, 0x00 /* NO SMIs */
+ .byte 0xc3, 0x14 /* Enable CPU config register */
+ .byte 0x20, 0x00
+ .byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */
+ .byte 0xc2, 0x00
+ .byte 0xe8, 0x98
+ .byte 0xc3, 0xf8 /* Enable CPU config register */
+cpu_setup_len = (.-cpu_setup_table)/2
+
+cpu_setup_end:
+ nop
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/gx1def.h
freebios/src/northbridge/nsc/gx1/gx1def.h
--- freebios.orig/src/northbridge/nsc/gx1/gx1def.h Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/gx1def.h Fri Mar 15 08:53:51 2002
@@ -0,0 +1,52 @@
+/*
+ freebios/src/northbridge/nsc/gx1/gx1def.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Defines for the GX1 processor
+*/
+
+/**********************************************************************/
+/* Display Controller Registers, offset from GX_BASE */
+
+#define DC_UNLOCK 0x8300
+#define DC_UNLOCK_MAGIC 0x4758
+
+#define DC_GENERAL_CFG 0x8304
+
+/**********************************************************************/
+/* Bus Controller Registers, offset from GX_BASE */
+
+#define BC_DRAM_TOP 0x8000
+
+#define BC_XMAP_1 0x8004
+#define BC_XMAP_2 0x8008
+#define BC_XMAP_3 0x800c
+
+/**********************************************************************/
+/* Memory Controller Registers, offset from GX_BASE */
+
+#define MC_MEM_CNTRL1 0x8400
+#define SDCLKSTRT (1<<17)
+#define RFSHRATE (0x1ff<<8)
+#define RFSHSTAG (0x3<<6)
+#define X2CLKADDR (1<<5)
+#define RFSHTST (1<<4)
+#define XBUSARB (1<<3)
+#define SMM_MAP (1<<2)
+#define PROGRAM_SDRAM (1<<0)
+
+#define MC_MEM_CNTRL2 0x8404
+#define SDCLK_MASK 0x000003c0
+#define SDCLKOUT_MASK 0x00000400
+
+#define MC_BANK_CFG 0x8408
+#define DIMM_PG_SZ 0x00000070
+#define DIMM_SZ 0x00000700
+#define DIMM_COMP_BNK 0x00001000
+#define DIMM_MOD_BNK 0x00004000
+
+#define MC_SYNC_TIM1 0x840c
+
+#define MC_GBASE_ADD 0x8414
+
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/gx_setup.inc
freebios/src/northbridge/nsc/gx1/gx_setup.inc
--- freebios.orig/src/northbridge/nsc/gx1/gx_setup.inc Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/gx_setup.inc Fri Mar 15 09:20:55 2002
@@ -0,0 +1,49 @@
+/*
+ freebios/src/northbridge/nsc/gx1/gx_setup.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Setup the GX_BASE registers on a National Semiconductor Geode CPU
+*/
+
+#include "gx1def.h"
+
+gx_setup_start:
+ leal gx_setup_table, %esi
+ movl $gx_setup_len, %ecx
+ movl $GX_BASE, %edi
+
+gx_setup_loop:
+ movw (%esi), %di /* Only read the low word of address */
+ addl $4, %esi
+ movl (%esi), %eax /* Data */
+ addl $4, %esi
+ movl %eax, (%edi)
+ loop gx_setup_loop
+
+ jmp gx_setup_end
+
+gx_setup_table:
+ /* Allow writes to config registers */
+ .long DC_UNLOCK, DC_UNLOCK_MAGIC
+ .long DC_GENERAL_CFG, 0
+ .long DC_UNLOCK, 0
+
+ .long BC_DRAM_TOP, 0x3fffffff
+ .long BC_XMAP_1, 0x60
+ .long BC_XMAP_2, 0
+ .long BC_XMAP_3, 0
+
+ .long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */
+ .long MC_MEM_CNTRL1, XBUSARB
+ .long MC_GBASE_ADD, 0x7ff /* Almost 1GB */
+gx_setup_len = (.-gx_setup_table)/8
+
+gx_setup_end:
+ nop
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/northbridge.c
freebios/src/northbridge/nsc/gx1/northbridge.c
--- freebios.orig/src/northbridge/nsc/gx1/northbridge.c Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/northbridge.c Fri Mar 15 09:20:55 2002
@@ -0,0 +1,82 @@
+/*
+ freebios/src/northbridge/nsc/gx1/northbridge.c
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Do chipset setup for a National Semiconductor GX1 CPU.
+*/
+
+#include <printk.h>
+#include <pci.h>
+#include <pci_ids.h>
+
+#include "gx1def.h"
+
+#define __io_virt(addr) (addr)
+
+#define readb(addr) (*(volatile unsigned char *) __io_virt(addr))
+#define readw(addr) (*(volatile unsigned short *) __io_virt(addr))
+#define readl(addr) (*(volatile unsigned int *) __io_virt(addr))
+
+#define writeb(b,addr) (*(volatile unsigned char *) __io_virt(addr) = (b))
+#define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b))
+#define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b))
+
+static unsigned calc_dimm(int index, unsigned cfg)
+{
+ if (((cfg >> 4) & 7) == 7) {
+ printk_info("DIMM%d: empty\n", index);
+ return 0;
+ } else {
+ unsigned page_size = 1 << ((cfg >> 4) & 7);
+ unsigned dimm_size = 4 << ((cfg >> 8) & 7);
+ unsigned comp_bank = 2 << ((cfg >> 12) & 1);
+ unsigned module_bank = 1 << ((cfg >> 14) & 1);
+
+ printk_info("DIMM%d: %uMB (%ukB page size, %d component banks, %u
+module banks)\n",
+ index, dimm_size, page_size, comp_bank, module_bank);
+ return dimm_size * 1024;
+ }
+}
+
+static unsigned long adjust_video_memory(unsigned long mem_size)
+{
+ unsigned video_size = 4096;
+
+ printk_info("Reserving %dkB for video memory\n", video_size);
+
+ /* Adjust for video memory size */
+ mem_size -= video_size;
+
+ /* Set up the registers */
+ writel(mem_size * 1024 - 1, GX_BASE + BC_DRAM_TOP);
+ writel(mem_size / 512, GX_BASE + MC_GBASE_ADD);
+
+ printk_debug("BC_DRAM_TOP = 0x%08x\n", readl(GX_BASE + BC_DRAM_TOP));
+ printk_debug("MC_GBASE_ADD = 0x%08x\n", readl(GX_BASE + MC_GBASE_ADD));
+
+ return mem_size;
+}
+
+unsigned long sizeram()
+{
+ u32 mem_bank_cfg;
+ unsigned mem_size;
+
+ mem_bank_cfg = *(volatile unsigned long *)(GX_BASE+0x8408);
+
+ mem_size = 0;
+ mem_size += calc_dimm(0, mem_bank_cfg);
+ mem_size += calc_dimm(1, mem_bank_cfg >> 16);
+
+ mem_size = adjust_video_memory(mem_size);
+
+ return mem_size;
+}
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ c-basic-offset: 8
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/northbridge_setup.inc
freebios/src/northbridge/nsc/gx1/northbridge_setup.inc
--- freebios.orig/src/northbridge/nsc/gx1/northbridge_setup.inc Thu Jan 1 01:00:00
1970
+++ freebios/src/northbridge/nsc/gx1/northbridge_setup.inc Fri Mar 15 09:20:55
+2002
@@ -0,0 +1,48 @@
+/*
+ freebios/src/northbridge/nsc/gx1/bridge_setup.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Setup the northbridge of a National Semiconductor GX1 CPU.
+*/
+
+northbridge_setup:
+ leal northbridge_setup_table, %esi
+ movl $northbridge_setup_len, %ecx
+ movl $0x80000000, %ebx /* Host Bridge Config Space */
+
+northbridge_setup_loop:
+ movb (%esi), %bl
+ incl %esi
+ movb (%esi), %al
+ incl %esi
+
+ movw $0xcf8, %dx /* PCI Write Config Byte */
+ xchgl %ebx, %eax
+ outl %eax, %dx
+ movw %ax, %dx
+ andw $3, %dx
+ orw $0xcfc, %dx
+ xchgl %ebx, %eax
+ outb %al, %dx
+
+ loop northbridge_setup_loop
+
+ jmp northbridge_setup_end
+
+northbridge_setup_table:
+ /* I belive this optimizes for X-bus performance */
+ .byte 0x40, 0x1e
+ .byte 0x41, 0x52
+ .byte 0x43, 0xc1 /* PCI arbitration 1 */
+ .byte 0x44, 0x00 /* PCI arbitration 2 */
+northbridge_setup_len = (.-northbridge_setup_table)/2
+
+northbridge_setup_end:
+ nop
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/northbridge/nsc/gx1/raminit.inc
freebios/src/northbridge/nsc/gx1/raminit.inc
--- freebios.orig/src/northbridge/nsc/gx1/raminit.inc Thu Jan 1 01:00:00 1970
+++ freebios/src/northbridge/nsc/gx1/raminit.inc Fri Mar 15 09:20:55 2002
@@ -0,0 +1,454 @@
+/*
+ freebios/src/northbridge/nsc/gx1/raminit.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Do memory sizing for a National Semiconductor GX1 CPU.
+*/
+
+#include "gx1def.h"
+
+/**********************************************************************/
+
+#define TEST_DATA1 0x05A5A5A5A
+#define TEST_DATA2 0x0DEADBEEF
+
+#define NUM_REFRESH 8
+
+/**********************************************************************/
+
+ram_setup:
+ CONSOLE_DEBUG_TX_STRING($str_setup_default_memory)
+
+ /* Set up Memory controller, note that all the code below
+ assumes that the high word of %edi contains GX_BASE */
+ movl $GX_BASE, %edi
+
+ movw $MC_MEM_CNTRL2, %di
+ movl $0x000007d8, (%edi) /* Disable all SDCLKs, Shift = 3 */
+
+ movw $MC_MEM_CNTRL1, %di
+ movl $0x92140000, (%edi) /* MD_DS=2, MA_DS=2, CNTL_DS=2
+ SDCLKRATE=/4 */
+
+ movw $MC_BANK_CFG, %di
+ movl $0x00700070, (%edi) /* No DIMMS installed */
+
+ movw $MC_SYNC_TIM1, %di
+ movl $0x3A733225, (%edi) /* LTMODE 3, RC 10, RAS 7, RP 3,
+ RCD 3, RRD 2, DPL 2 */
+
+ movw $MC_BANK_CFG, %di
+ movl $0x57405740, (%edi) /* Largest possible DIMMS installed
+ 0x4000 -- 2 module banks
+ 0x1000 -- 4 component banks
+ 0x0700 -- DIMM size 512MB
+ 0x0040 -- Page Size 16kB */
+
+ CALLSP(enable_dimm) /* Program the DIMM's */
+
+ CONSOLE_DEBUG_TX_STRING($str_sizing_memory)
+
+ /* EBP will contain the DIMM configuration after we're done.
+ To begin with, it is set up for no DIMMs at all */
+ movl $0x00700070, %ebp
+
+ /* Parameters for DIMM0 */
+ movl $0x00705740, %edx /* DIMM0 is maxed, no DIMM0 */
+ movb $0, %cl /* Shift value DIMM0=0, DIMM1=16 */
+
+dimm_loop:
+ movl %edx, %esi
+ CONSOLE_INFO_TX_STRING($str_probing)
+ movb %cl, %al
+ rorb $4, %al
+ addb $'0', %al
+ CONSOLE_INFO_TX_CHAR(%al)
+ CONSOLE_INFO_TX_STRING($str_nl)
+ movl %esi, %edx
+
+ /* First configure the memory with the new settings */
+ movw $MC_BANK_CFG, %di
+ movl %edx, (%edi)
+ CALLSP(do_refresh)
+
+ /* Write something to location 0 and read it back */
+ movl $TEST_DATA1, 0 /* Write data to location 0 */
+ movl $0, 0x100 /* Clear the bus */
+ movl 0, %eax /* Read data from location 0 */
+ movl $0, 0 /* Clear location 0 */
+
+ /* If we got the same value back, there is memory in the bank */
+ cmpl $TEST_DATA1, %eax
+ jne next_dimm
+
+ movl $TEST_DATA2, 0 /* Write data to location 0 */
+ movl $0, 0x100 /* Clear the bus */
+ movl 0, %eax /* Read data from location 0 */
+ movl $0, 0 /* Clear location 0 */
+
+ cmpl $TEST_DATA2, %eax
+ jne next_dimm
+
+#ifdef DEBUG
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_found)
+ movb %cl, %al
+ rorb $4, %al
+ addb $'0', %al
+ CONSOLE_DEBUG_TX_CHAR(%al)
+ CONSOLE_DEBUG_TX_STRING($str_nl)
+ movl %esi, %edx
+#endif
+
+/* Do page size detection, read the NatSemi reference drivers for an
+ explanation of how it works */
+
+ movl $0x0040, %ebx /* MC_BANK_CFG for 16kB page size */
+ movl $0x2000, %esi /* Offset: 16kB/2 */
+
+page_size_loop:
+ movl $TEST_DATA1, 0 /* Write data to location 0 */
+ movl $TEST_DATA2, (%esi) /* Write to page size/2 */
+ movl $0, 0x100 /* Clear the bus */
+ movl 0, %eax /* Read data from location 0 */
+ movl $0, 0 /* Clear location 0 */
+
+ cmpl $TEST_DATA1, %eax /* If no aliasing, we have found */
+ je page_size_found /* out the page size */
+
+ /* We had aliasing, so go to the next smaller setting */
+ movw $MC_BANK_CFG, %di
+ movl (%edi), %edx /* Get current MC_BANK_CFG settings */
+ movl $~DIMM_PG_SZ, %eax /* Mask for the page size */
+ roll %cl, %eax /* Shift for the right DIMM */
+ andl %eax, %edx /* Do the masking */
+ subl $0x10,%ebx /* Select the next smaller page size */
+ jc mem_sizing_failed /* Nothing matched, we've failed */
+ shll %cl, %ebx /* Shift for the right DIMM */
+ orl %ebx, %edx /* And merge it into the settings */
+ shrl %cl, %ebx /* And shift it back again */
+ shrl $1, %esi /* Divide test address by 2 */
+
+ movl %edx, (%edi) /* Use the new MC_BANK_CFG settings */
+ CALLSP(do_refresh)
+ jmp page_size_loop
+
+page_size_found:
+ /* Save the page size we found in EBP */
+ movl $~DIMM_PG_SZ, %eax
+ roll %cl, %eax
+ andl %eax, %ebp
+ movl %ebx, %eax
+ shll %cl, %eax
+ or %eax, %ebp
+
+#ifdef DEBUG
+ shll $1, %esi
+ movw %si, %di
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_page_size)
+ xorl %eax, %eax
+ movw %di, %ax
+ CONSOLE_DEBUG_TX_HEX32(%eax)
+ CONSOLE_DEBUG_TX_STRING($str_nl)
+ movl %esi, %edx
+#endif
+
+/* Do component banks detection */
+ movl $0x0800, %esi /* Smallest page = 1KB * 2 banks */
+
+ shll $16, %ecx /* Save DIMM shift */
+ movl %ebp, %eax /* Get the DIMM values */
+ shrl %cl, %eax /* shifted back */
+
+ movw %ax, %cx /* Use the MC_BANK_CFG */
+ shrw $4, %cx /* page size setting as */
+ andb $7, %cl /* a shift to calculate */
+ shll %cl, %esi /* the page size */
+
+ shrl $16, %ecx /* Restore DIMM shift */
+
+ movl $TEST_DATA1, 0 /* Write data to location 0 */
+ movl $TEST_DATA2, (%esi) /* Write to next page */
+ movl $0, 0x100 /* Clear the bus */
+ movl 0, %eax /* Read data from location 0 */
+
+ cmpl $TEST_DATA1, %eax /* If no aliasing, */
+ je component_banks_4 /* there are 4 banks */
+
+ /* Reconfigure the memory controller for 2 banks */
+ movw $MC_BANK_CFG, %di
+ movl (%edi), %edx
+ movl $~DIMM_COMP_BNK, %eax /* Mask for component banks */
+ roll %cl, %eax /* shifted */
+ andl %eax, %ebp /* clear the bit of EBP */
+ andl %eax, %edx /* clear the bit of EDX */
+ movl %edx, (%edi) /* Use new settings */
+ CALLSP(do_refresh)
+#ifdef DEBUG
+ movw $'2',%di
+#endif
+ jmp component_banks_done
+
+component_banks_4:
+ movl $DIMM_COMP_BNK, %eax /* Set the bit of EBP */
+ roll %cl, %eax /* shifted */
+ orl %eax, %ebp
+#ifdef DEBUG
+ movw $'4',%di
+#endif
+component_banks_done:
+#ifdef DEBUG
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_component_banks)
+ movw %di, %ax
+ CONSOLE_DEBUG_TX_CHAR(%al)
+ CONSOLE_DEBUG_TX_STRING($str_nl)
+ movl %esi, %edx
+#endif
+
+/* Do module banks detection */
+ movl $0x0800, %esi /* Smallest page = 1KB * 2 banks */
+
+ shll $16, %ecx /* Save DIMM shift */
+ movl %ebp, %eax /* Get the DIMM values */
+ shrl %cl, %eax /* shifted back */
+
+ movw %ax, %cx /* Use the MC_BANK_CFG */
+ shrw $4, %cx /* page size setting as */
+ andb $7, %cl /* a shift to calculate */
+ shll %cl, %esi /* the page size */
+
+ movw %ax, %cx /* Use the MC_BANK_CFG */
+ shrw $12, %cx /* component bank setting */
+ andb $1, %cl /* a shift to calculate */
+ shll %cl, %esi /* the total bank size */
+
+ shrl $16, %ecx /* Restore DIMM shift */
+
+ movl $TEST_DATA1, 0 /* Write data to location 0 */
+ movl $TEST_DATA2, (%esi) /* Write to module bank 2 */
+ movl $0, 0x100 /* Clear the bus */
+ movl (%esi), %eax /* Read from module bank 2 */
+
+ cmpl $TEST_DATA2, %eax /* If good data, */
+ je module_banks_2 /* there are 2 module banks */
+
+ /* Reconfigure the memory controller for 1 module bank */
+ movw $MC_BANK_CFG, %di
+ movl (%edi), %edx
+ movl $~DIMM_MOD_BNK, %eax /* Mask for module banks */
+ roll %cl, %eax /* shifted */
+ andl %eax, %ebp /* clear the bit of EBP */
+ andl %eax, %edx /* clear the bit of EDX */
+ movl %edx, (%edi) /* Use new settings */
+ CALLSP(do_refresh)
+#ifdef DEBUG
+ movw $'1',%di
+#endif
+ jmp module_banks_done
+
+module_banks_2:
+ movl $DIMM_MOD_BNK, %eax /* Set the bit of EBP */
+ roll %cl, %eax /* shifted */
+ orl %eax, %ebp
+#ifdef DEBUG
+ movw $'2',%di
+#endif
+module_banks_done:
+#ifdef DEBUG
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_module_banks)
+ movw %di, %ax
+ CONSOLE_DEBUG_TX_CHAR(%al)
+ CONSOLE_DEBUG_TX_STRING($str_nl)
+ movl %esi, %edx
+#endif
+
+/* Finally, figure out the size of the DIMM */
+ movl $0x0700, %ebx /* MC_BANK_CFG for 512MB */
+ movl $0x10000000, %esi /* Offset: 256MB */
+
+dimm_size_loop:
+ movl $TEST_DATA1, 0 /* Write data to location 0 */
+ movl $TEST_DATA2, (%esi) /* Write to memory size/2 */
+ movl $0, 0x100 /* Clear the bus */
+ movl 0, %eax /* Read data from location 0 */
+ movl $0, 0 /* Clear location 0 */
+
+ cmpl $TEST_DATA1, %eax /* If no aliasing, we have found */
+ je dimm_size_found /* out the memory size */
+
+ /* We had aliasing, so go to the next smaller setting */
+ movw $MC_BANK_CFG, %di
+ movl (%edi), %edx /* Get current MC_BANK_CFG settings */
+ movl $~DIMM_SZ, %eax /* Mask for the DIMM size */
+ roll %cl, %eax /* Shift for the right DIMM */
+ and %eax, %edx /* Do the masking */
+ decb %bh /* Halve the memory size */
+ jc mem_sizing_failed /* Nothing matched, we've failed */
+ shll %cl, %ebx /* Shift for the right DIMM */
+ orl %ebx, %edx /* And merge it into the settings */
+ shrl %cl, %ebx /* And shift it back again */
+ shrl $1, %esi /* Divide test address by 2 */
+
+ movl %edx, (%edi) /* Use the new MC_BANK_CFG settings */
+ CALLSP(do_refresh)
+ jmp dimm_size_loop
+
+dimm_size_found:
+ /* Save the page size we found in EBP */
+ movl $~DIMM_SZ, %eax
+ roll %cl, %eax
+ andl %eax, %ebp
+ movl %ebx, %eax
+ shll %cl, %eax
+ or %eax, %ebp
+
+ shrl $16-1, %esi
+ movw %si, %di
+ movl %edx, %esi
+ CONSOLE_INFO_TX_STRING($str_dimm_size)
+ movw %di, %ax
+ shll $16, %eax
+ CONSOLE_INFO_TX_HEX32(%eax)
+ CONSOLE_INFO_TX_STRING($str_nl)
+ movl %esi, %edx
+
+next_dimm:
+ movl $0x12345678, 0 /* Write garbage to location 0 */
+
+ addb $16, %cl
+ movl $0x57400070, %edx /* No DIMM0, DIMM1 is maxed */
+
+ /* Try the two shift values 0, and 16 */
+ cmpb $32, %cl
+ jne dimm_loop
+
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_done)
+ CONSOLE_DEBUG_TX_HEX32(%ebp)
+ CONSOLE_DEBUG_TX_STRING($str_nl)
+ movl %esi, %edx
+
+ /* Finally use the MC_BANK_CFG settings we've calculated */
+ movw $MC_BANK_CFG, %di
+ movl %ebp, (%edi)
+
+ jmp ram_setup_end
+
+mem_sizing_failed:
+#ifdef DEBUG
+ movl %edx, %esi
+ CONSOLE_DEBUG_TX_STRING($str_failed)
+ movl %esi, %edx
+#endif
+ movl $0xffff0000, %eax
+ roll %cl, %eax
+ andl %eax, %ebp
+ movl $0x00000070, %eax
+ shll %cl, %eax
+ orl %eax, %ebp
+
+ jmp next_dimm
+
+str_setup_default_memory:
+ .string "Setting up default parameters for memory\r\n"
+str_sizing_memory:
+ .string "Sizing memory\r\n"
+str_sizing_done:
+ .string "Sizing done\r\n"
+str_done:
+ .string "Memory sizing done, MC_BANK_CFG = 0x"
+str_probing:
+ .string "Probing for DIMM"
+str_found:
+ .string " Found DIMM"
+str_failed:
+ .string " Failed to identify DIMM"
+str_page_size:
+ .string " Page Size: "
+str_component_banks:
+ .string " Component Banks: "
+str_module_banks:
+ .string " Module Banks: "
+str_dimm_size:
+ .string " DIMM size: "
+str_nl:
+ .string "\r\n"
+
+/**********************************************************************/
+/* all these functions assume that the upper word of EDI contains
+ GX_BASE */
+
+/* Destroys EAX, high word of ECX and low word of EDI */
+do_refresh:
+ shll $16, %ecx /* save CX */
+ movw $MC_MEM_CNTRL1, %di
+ movl (%edi), %eax
+ orb $RFSHTST, %al
+ movw $NUM_REFRESH, %cx
+1: movl %eax, (%edi)
+ loopw 1b
+ andb $~RFSHTST, %al
+ movl %eax, (%edi)
+ shrl $16, %ecx /* restore CX */
+ RETSP
+
+enable_dimm:
+ /* Start the SDCLK's */
+ movw $MC_MEM_CNTRL1, %di
+ movl (%edi), %eax
+ andl $~SDCLKSTRT, %eax
+ movl %eax, (%edi)
+ orl $SDCLKSTRT, %eax
+ movl %eax, (%edi)
+
+ /* Unmask the SDCLK's */
+ movw $MC_MEM_CNTRL2, %di
+ movl (%edi), %eax
+ andl $~(SDCLK_MASK | SDCLKOUT_MASK), %eax
+ movl %eax, (%edi)
+
+ movw $5000, %cx /* Wait for clocks to unmask */
+1: outb %al, $0xed
+ loopw 1b
+
+ movw $MC_MEM_CNTRL1, %di /* Refresh memory */
+ movl (%edi), %eax
+ orb $RFSHTST, %al
+ movw $NUM_REFRESH, %cx
+1: movl %eax, (%edi)
+ loopw 1b
+ andb $~RFSHTST, %al
+
+ /* Start the SDCLK's */
+ andl $~PROGRAM_SDRAM, %eax
+ movl %eax, (%edi)
+ orl $PROGRAM_SDRAM | 0x00002000, %eax /* Set refresh timing */
+ movl %eax, (%edi)
+ andl $~PROGRAM_SDRAM, %eax
+ movl %eax, (%edi)
+
+ movl (%edi), %eax /* Refresh memory again */
+ orb $RFSHTST, %al
+ movw $NUM_REFRESH, %cx
+1: movl %eax, (%edi)
+ loopw 1b
+
+ movw $2000, %cx
+1: outb %al, $0xed
+ loopw 1b
+
+ RETSP
+
+/**********************************************************************/
+
+ram_setup_end:
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/southbridge/nsc/cs5530/Config
freebios/src/southbridge/nsc/cs5530/Config
--- freebios.orig/src/southbridge/nsc/cs5530/Config Thu Jan 1 01:00:00 1970
+++ freebios/src/southbridge/nsc/cs5530/Config Fri Mar 15 09:22:46 2002
@@ -0,0 +1,7 @@
+# freebios/src/southbridge/nsc/cs5530/Config
+# Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+# Config file for the National Semiconductor CS5530 southbridge
+# a.k.a. companion chip
+
+object southbridge.o
+
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/southbridge/nsc/cs5530/southbridge.c
freebios/src/southbridge/nsc/cs5530/southbridge.c
--- freebios.orig/src/southbridge/nsc/cs5530/southbridge.c Thu Jan 1 01:00:00
1970
+++ freebios/src/southbridge/nsc/cs5530/southbridge.c Fri Mar 15 09:22:46 2002
@@ -0,0 +1,92 @@
+/*
+ freebios/src/southbridge/nsc/cs5530/southbridge.c
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Configure the National Semiconductor CS5530 southbridge
+*/
+
+#include <printk.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <cpu/p5/io.h>
+
+#include <types.h>
+
+#define NAME "cs5530: "
+
+void nvram_on()
+{
+}
+
+void final_southbridge_fixup()
+{
+ struct pci_dev *dev;
+ u8 b;
+ u16 int_map;
+ int inta, intb, intc, intd;
+ u16 trig;
+
+ printk_info("Final southbridge fixup\n");
+
+ dev = pci_find_device(PCI_VENDOR_ID_CYRIX,
+ PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+ (void *)NULL);
+ if (!dev) {
+ printk_warning(NAME "Can't find PCI bridge\n");
+ return;
+ }
+
+ pci_read_config_word(dev, 0x5c, &int_map);
+ printk_debug("F0/5c: 0x%04x\n", int_map);
+ inta = CS5530_INTA;
+ intb = CS5530_INTB;
+ intc = CS5530_INTC;
+ intd = CS5530_INTD;
+ printk_info(NAME "PCI INTA=%d, INTB=%d, INTC=%d, INTD=%d\n",
+ inta, intb, intc, intd);
+ int_map = inta | (intb<<4) | (intc<<8) | (intd<<12);
+ pci_write_config_word(dev, 0x5c, int_map);
+
+ pci_read_config_word(dev, 0x5c, &int_map);
+ printk_debug("F0/5c: 0x%04x\n", int_map);
+
+ /* All PCI interrupts are level trigged, the rest are edge trigged */
+ printk_debug("4d0: 0x%02x\n", inb(0x4d0));
+ printk_debug("4d1: 0x%02x\n", inb(0x4d1));
+ trig = 0;
+ if (inta) trig |= (1<<inta);
+ if (intb) trig |= (1<<intb);
+ if (intc) trig |= (1<<intc);
+ if (intd) trig |= (1<<intd);
+ outb(trig, 0x4d0);
+ outb(trig >> 8, 0x4d1);
+ printk_debug("4d0: 0x%02x\n", inb(0x4d0));
+ printk_debug("4d1: 0x%02x\n", inb(0x4d1));
+
+ pci_read_config_byte(dev, 0x5b, &b);
+ printk_debug("F0/5b = 0x%02x\n", b);
+#ifdef CS5530_PRIMARY_IDE
+ printk_info(NAME "Enabling Primary IDE Controller\n");
+ b |= 1<<3;
+#endif
+#ifdef CS5530_SECONDARY_IDE
+ printk_info(NAME "Enabling Secondary IDE Controller\n");
+ b |= 1<<4;
+#endif
+ printk_debug("F0/5b = 0x%02x\n", b);
+ pci_write_config_byte(dev, 0x5b, b);
+
+ dev = pci_find_slot(0, PCI_DEVFN(0x13, 0));
+ if (dev) {
+ printk_debug(NAME "USB is on INTA, IRQ %d\n", inta);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, inta);
+ }
+}
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ c-basic-offset: 8
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/southbridge/nsc/scx200/Config
freebios/src/southbridge/nsc/scx200/Config
--- freebios.orig/src/southbridge/nsc/scx200/Config Thu Jan 1 01:00:00 1970
+++ freebios/src/southbridge/nsc/scx200/Config Fri Mar 15 09:22:46 2002
@@ -0,0 +1,4 @@
+# freebios/src/southbridge/nsc/scx200/Config
+# Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+object southbridge.o
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/southbridge/nsc/scx200/scx200_setup.inc
freebios/src/southbridge/nsc/scx200/scx200_setup.inc
--- freebios.orig/src/southbridge/nsc/scx200/scx200_setup.inc Thu Jan 1 01:00:00
1970
+++ freebios/src/southbridge/nsc/scx200/scx200_setup.inc Fri Mar 15 09:22:46
+2002
@@ -0,0 +1,268 @@
+/*
+ freebios/src/northsouthbridge/NSC/scx200/chipset_setup.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Do chipset setup for a National Semiconductor SCx200 CPU.
+*/
+
+/**********************************************************************/
+
+scx200_setup_start:
+/* Configure F0 */
+ movl $f0_setup_table, %esi
+ movl $f0_setup_len, %ecx
+ movl $0x80009000, %ebx /* F0 Config Space */
+
+f0_setup_loop:
+ movb (%esi), %bl
+ CALLSP(scx200_pci_read_config_byte)
+ incl %esi
+ andb (%esi), %al
+ incl %esi
+ orb (%esi), %al
+ CALLSP(scx200_pci_write_config_byte)
+ incl %esi
+ loopl f0_setup_loop
+
+/* Configure F5 */
+ movl $f5_setup_table, %esi
+ movl $f5_setup_len, %ecx
+ movl $0x80009500, %ebx /* F5 Config Space */
+
+f5_setup_loop:
+ movb (%esi), %bl
+ CALLSP(scx200_pci_read_config_byte)
+ incl %esi
+ andb (%esi), %al
+ incl %esi
+ orb (%esi), %al
+ CALLSP(scx200_pci_write_config_byte)
+ incl %esi
+ loopl f5_setup_loop
+
+/* Configure the SIO address */
+ movw $0x6200, %dx /* I/O Control Register */
+ inl %dx, %eax
+ movl $0x0f040000, %eax /* SIO at 0x15c, Enable USB */
+ outl %eax, %dx
+
+ movw $0x15c, %dx /* Super I/O */
+ movb $0x20, %al /* Index 0x20, SIO Config */
+ outb %al, %dx
+ xorw $1, %dx
+ inb %dx, %al
+ cmpb $0xf5, %al /* SIO ID */
+ jnz scx200_setup_start
+
+config_block_setup:
+ movw $0x2ea, %dx /* initial register to set address */
+ movw $SCx200_CB_BASE, %ax /* Config Block Base Address */
+ outw %ax, %dx
+
+ movw $SCx200_CB_BASE, %bx /* Config Block Base Address */
+ movw %bx, %dx
+ addw $0x30, %dx /* PMR */
+ movl $SCx200_PMR, %eax
+ outl %eax, %dx
+ movw %bx, %dx
+ addw $0x34, %dx /* MCR */
+ movl $SCx200_MCR, %eax
+ outl %eax, %dx
+ movw %bx, %dx
+ addw $0x12, %dx /* PPCR */
+ inb %dx, %al
+ andb $0xd1, %al /* Enable PLLs */
+ outb %al, %dx
+
+#if 0
+ /* But this stops the serial port from working. */
+ movw %bx, %dx
+ addw $0x18, %dx /* PLL3 */
+ movl $0x7601d004, %eax /* Must be programmed with this */
+ outl %eax, %dx /* value according to databook */
+#endif
+
+#ifdef WATCHDOG_INIT
+watchdog_setup:
+ movw $SCx200_CB_BASE, %bx /* Config Block Base Address */
+ movw %bx, %dx
+ addw $0x2, %dx /* WDCNFG */
+ movw $0xfa, %ax /* enable watchdog */
+ outw %ax, %dx
+ movw %bx, %dx /* WDTO */
+ movw $32*(WATCHDOG_INIT), %ax
+ outw %ax, %dx
+#endif
+
+/* RTC setup */
+ movw $0x70, %dx
+ movb $0x0d, %al
+ outb %al, %dx
+ movw $0x71, %dx
+ inb %dx, %al
+ inb %dx, %al
+ movw $0x70, %dx
+ movb $0x0b, %al
+ outb %al, %dx
+ movw $0x71, %dx
+ movb $0x02, %al
+ outb %al, %dx
+
+/* GPIO setup */
+ /* FIXME ought to do GPIO setup here */
+
+/* Configure the SIO itself */
+ lea sio_setup_table, %esi
+ movl $sio_setup_size, %ecx
+ mov $0x15c, %dx
+
+sio_setup_loop:
+ movb (%esi), %al
+ incl %esi
+ outb %al, %dx
+ xorb $1, %dl
+ loop sio_setup_loop
+
+ jmp scx200_setup_end
+
+scx200_pci_read_config_byte:
+ movw $0xcf8, %dx
+ movl %ebx, %eax
+ outl %eax, %dx
+ movw %ax, %dx
+ andw $3, %dx
+ orw $0xcfc, %dx
+ inb %dx, %al
+ RETSP
+
+scx200_pci_write_config_byte:
+ movw $0xcf8, %dx
+ xchgl %ebx, %eax
+ outl %eax, %dx
+ movw %ax, %dx
+ andw $3, %dx
+ orw $0xcfc, %dx
+ xchgl %ebx, %eax
+ outb %al, %dx
+ RETSP
+
+f0_setup_table:
+ .byte 0x10, 0x00, 0x01 /* F0BAR0/GPIO = 0x00006401 */
+ .byte 0x11, 0x00, 0x64
+ .byte 0x12, 0x00, 0x00
+ .byte 0x13, 0x00, 0x00
+
+ .byte 0x47, 0xfb, 0x06 /* Enable F0BAR0/GPIO, F0BAR1/LPC */
+ .byte 0x5a, 0x00, 0x01 /* Enable RTC Positive Decode */
+ .byte 0x5b, 0x00, 0x01 /* Enable LPC Positive Decode */
+
+#ifdef SCx200_DOCCS_BASE
+ .byte 0x78, 0x00, (SCx200_DOCCS_BASE>>0)&0xff
+ .byte 0x79, 0x00, (SCx200_DOCCS_BASE>>8)&0xff
+ .byte 0x7a, 0x00, (SCx200_DOCCS_BASE>>16)&0xff
+ .byte 0x7b, 0x00, (SCx200_DOCCS_BASE>>24)&0xff
+
+ .byte 0x7c, 0x00, (SCx200_DOCCS_CTRL>>0)&0xff
+ .byte 0x7d, 0x00, (SCx200_DOCCS_CTRL>>8)&0xff
+ .byte 0x7e, 0x00, (SCx200_DOCCS_CTRL>>16)&0xff
+ .byte 0x7f, 0x00, (SCx200_DOCCS_CTRL>>24)&0xff
+#endif
+
+ .byte 0x43, 0xff, 0x80 /* Must be set to 1 */
+ .byte 0x43, 0xfd, 0x00 /* Speed up PIT accesses */
+
+f0_setup_len = (.-f0_setup_table) / 3
+
+f5_setup_table:
+ .byte 0x40, 0x00, 0xc1 /* F5BAR0 Mask = 0xffffffc1 */
+ .byte 0x41, 0x00, 0xff
+ .byte 0x42, 0x00, 0xff
+ .byte 0x43, 0x00, 0xff
+
+ .byte 0x10, 0x00, 0x01 /* F5BAR0/X-Bus = 0x00006201 */
+ .byte 0x11, 0x00, 0x62
+ .byte 0x12, 0x00, 0x00
+ .byte 0x13, 0x00, 0x00
+
+ .byte 0x04, 0x00, 0x03 /* Enable F5 Memory and I/O Space */
+f5_setup_len = (.-f5_setup_table) / 3
+
+sio_setup_table:
+ .byte 0x07, 0x00 /* Device 0 -- RTC */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x70, 0x08 /* Use IRQ 8 */
+ .byte 0x30, 0x01 /* Enable */
+
+
+ .byte 0x07, 0x01 /* Device 1 -- System Wake-Up Ctrl */
+ .byte 0x60, 0x08 /* I/O Base Address 0x860 */
+ .byte 0x61, 0x60
+ .byte 0x30, 0x01 /* Enable */
+
+#ifdef SCx200_SP3_BASE
+ .byte 0x07, 0x02 /* Device 2 -- Serial port 3 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_SP3_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_SP3_BASE&0xff
+ .byte 0x70, SCx200_SP3_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SCx200_SP1_BASE
+ .byte 0x07, 0x03 /* Device 3 -- Serial port 1 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_SP1_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_SP1_BASE&0xff
+ .byte 0x70, SCx200_SP1_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SCx200_ACB1_BASE
+ .byte 0x07, 0x05 /* Device 5 -- ACCESS.bus 1 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_ACB1_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_ACB1_BASE&0xff
+ .byte 0x70, SCx200_ACB1_IRQ /* IRQ */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SCx200_ACB2_BASE
+ .byte 0x07, 0x05 /* Device 6 -- ACCESS.bus 2 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_ACB2_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_ACB2_BASE&0xff
+ .byte 0x70, SCx200_ACB2_IRQ /* IRQ */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SCx200_PP_BASE
+ .byte 0x07, 0x08 /* Device 7 -- Parallel Port */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_PP_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_PP_BASE&0xff
+ .byte 0x70, SCx200_PP_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SCx200_SP2_BASE
+ .byte 0x07, 0x08 /* Device 8 -- Serial port 2 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SCx200_SP2_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SCx200_SP2_BASE&0xff
+ .byte 0x70, SCx200_SP2_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+sio_setup_size = .-sio_setup_table
+
+scx200_setup_end:
+
+/*
+ Local variables:
+ compile-command: "make -C /export/nano/bios/nano"
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/southbridge/nsc/scx200/southbridge.c
freebios/src/southbridge/nsc/scx200/southbridge.c
--- freebios.orig/src/southbridge/nsc/scx200/southbridge.c Thu Jan 1 01:00:00
1970
+++ freebios/src/southbridge/nsc/scx200/southbridge.c Fri Mar 15 09:22:46 2002
@@ -0,0 +1,95 @@
+/*
+ freebios/src/southbridge/nsc/scx200/southbridge.c
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Configure the National Semiconductor SCx200 southbridge. This
+ chip is mostly the same as the CS5530 southbridge, but enough
+ things are different to warrant two different files.
+*/
+
+#include <printk.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <cpu/p5/io.h>
+
+#include <types.h>
+
+#define NAME "scx200: "
+
+void nvram_on()
+{
+}
+
+void final_southbridge_fixup()
+{
+ struct pci_dev *dev;
+ u8 b;
+ u16 int_map;
+ int inta, intb, intc, intd;
+ u16 trig;
+
+ printk_info("Final southbridge fixup\n");
+
+ dev = pci_find_device(PCI_VENDOR_ID_NS,
+ PCI_DEVICE_ID_NS_SCx200_BRIDGE,
+ (void *)NULL);
+ if (!dev) {
+ printk_warning(NAME "Can't find PCI bridge\n");
+ return;
+ }
+
+ pci_read_config_word(dev, 0x5c, &int_map);
+ printk_debug("F0/5c: 0x%04x\n", int_map);
+ inta = SCx200_INTA;
+ intb = SCx200_INTB;
+ intc = SCx200_INTC;
+ intd = SCx200_INTD;
+ printk_info(NAME "PCI INTA=%d, INTB=%d, INTC=%d, INTD=%d\n",
+ inta, intb, intc, intd);
+ int_map = inta | (intb<<4) | (intc<<8) | (intd<<12);
+ pci_write_config_word(dev, 0x5c, int_map);
+
+ pci_read_config_word(dev, 0x5c, &int_map);
+ printk_debug("F0/5c: 0x%04x\n", int_map);
+
+ /* All PCI interrupts are level trigged, the rest are edge trigged */
+ printk_debug("4d0: 0x%02x\n", inb(0x4d0));
+ printk_debug("4d1: 0x%02x\n", inb(0x4d1));
+ trig = 0;
+ if (inta) trig |= (1<<inta);
+ if (intb) trig |= (1<<intb);
+ if (intc) trig |= (1<<intc);
+ if (intd) trig |= (1<<intd);
+ outb(trig, 0x4d0);
+ outb(trig >> 8, 0x4d1);
+ printk_debug("4d0: 0x%02x\n", inb(0x4d0));
+ printk_debug("4d1: 0x%02x\n", inb(0x4d1));
+
+ pci_read_config_byte(dev, 0x5b, &b);
+ printk_debug("F0/5b = 0x%02x\n", b);
+#ifdef SCx200_PRIMARY_IDE
+ printk_info(NAME "Enabling Primary IDE Controller\n");
+ b |= 1<<3;
+#endif
+#ifdef SCx200_SECONDARY_IDE
+ printk_info(NAME "Enabling Secondary IDE Controller\n");
+ b |= 1<<4;
+#endif
+ printk_debug("F0/5b = 0x%02x\n", b);
+ pci_write_config_byte(dev, 0x5b, b);
+
+ dev = pci_find_slot(0, PCI_DEVFN(0x13, 0));
+ if (dev) {
+ printk_debug(NAME "USB is on INTD, IRQ %d\n", intd);
+ pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 4);
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, intd);
+ }
+}
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/nano"
+ c-basic-offset: 8
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/superio/NSC/pc97317/sio_setup.inc
freebios/src/superio/NSC/pc97317/sio_setup.inc
--- freebios.orig/src/superio/NSC/pc97317/sio_setup.inc Thu Jan 1 01:00:00 1970
+++ freebios/src/superio/NSC/pc97317/sio_setup.inc Fri Mar 15 08:58:27 2002
@@ -0,0 +1,145 @@
+/*
+ freebios/src/superio/NSC/pc97317/sio_setup.inc
+
+ Copyright (c) 2002 Christer Weinigel <[EMAIL PROTECTED]>
+
+ Set up a National Semiconductor PC97317 Super I/O
+*/
+
+#ifndef SIO_BASE
+#define SIO_BASE 0x2e
+#endif
+
+sio_boot:
+ lea sio_boot_table, %esi
+ movl $sio_boot_size, %ecx
+ movw $SIO_BASE, %dx
+
+sio_boot_loop:
+ movb (%esi), %al
+ incl %esi
+ outb %al, %dx
+ xorb $1, %dl
+ loop sio_boot_loop
+
+sio_rtc_boot:
+ movb $0x0a, %al /* RTC Control Register A */
+ outb %al, $0x70 /* RTC */
+ inb $0x71, %al
+ andb $0xf0, %al
+ orb $0x06, %al /* Interrupt rate */
+ outb %al, $0x71
+
+sio_wakeup:
+ movb $0x03, %al /* Use on chip clock multiplier */
+ outb %al, $0xe8
+ inb $0xe9, %al
+ orb $0x07, %al
+ outb %al, $0xe9
+
+sio_wakeup_wait:
+ inb $0xe9, %al /* Wait for the clock to stabilize */
+ testb $0x80, %al
+ jz sio_wakeup_wait
+
+sio_setup:
+ lea sio_setup_table, %esi
+ movl $sio_setup_size, %ecx
+ mov $SIO_BASE, %dx
+
+sio_setup_loop:
+ movb (%esi), %al
+ incl %esi
+ outb %al, %dx
+ xorb $1, %dl
+ loop sio_setup_loop
+
+sio_rtc_setup:
+ movb $0x0a, %al /* RTC Control Register A */
+ outb %al, $0x70
+ movb $0x26, %al /* Normal operation */
+ outb %al, $0x71
+
+ movw $0x70, %dx
+ movb $0x0d, %al
+ outb %al, %dx
+ movw $0x71, %dx
+ inb %dx, %al
+ inb %dx, %al
+ movw $0x70, %dx
+ movb $0x0b, %al
+ outb %al, %dx
+ movw $0x71, %dx
+ movb $0x02, %al
+ outb %al, %dx
+
+ jmp sio_setup_end
+
+sio_boot_table:
+ .byte 0x07, 0x08 /* LDN 8 -- Power Management */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, 0x00 /* Base High */
+ .byte 0x61, 0xe8 /* Base Low */
+ .byte 0x30, 0x01 /* Enable */
+sio_boot_size = .-sio_boot_table
+
+sio_setup_table:
+ .byte 0x07, 0x00 /* Device 0 -- Keyboard */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x70, 0x01 /* IRQ 1 */
+ .byte 0x30, 0x01 /* Enable */
+
+ .byte 0x07, 0x02 /* Device 2 -- RTC & APC */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x70, 0x08 /* IRQ 8 */
+ .byte 0x30, 0x01 /* Enable */
+
+#ifdef SIO_PP_BASE
+ .byte 0x07, 0x04 /* Device 4 -- Parallel Port */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SIO_PP_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SIO_PP_BASE&0xff
+ .byte 0x70, SIO_PP_IRQ /* IRQ */
+ .byte 0xf0, 0xf2 /* PP Configuration, ECP, enabled */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SIO_SP2_BASE
+ .byte 0x07, 0x05 /* Device 5 -- Serial port 2 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SIO_SP2_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SIO_SP2_BASE&0xff
+ .byte 0x70, SIO_SP2_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SIO_SP1_BASE
+ .byte 0x07, 0x06 /* Device 6 -- Serial port 1 */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SIO_SP1_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SIO_SP1_BASE&0xff
+ .byte 0x70, SIO_SP1_IRQ /* IRQ */
+ .byte 0xf0, 0x82 /* Serial Configuration Register */
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+#ifdef SIO_GPIO_BASE
+ .byte 0x07, 0x07 /* Device 7 -- GPIO Ports */
+ .byte 0x30, 0x00 /* Disable */
+ .byte 0x60, SIO_GPIO_BASE>>8 /* I/O Base Address */
+ .byte 0x61, SIO_GPIO_BASE&0xff
+ .byte 0x30, 0x01 /* Enable */
+#endif
+
+sio_setup_size = .-sio_setup_table
+
+sio_setup_end:
+ nop
+
+/*
+ Local variables:
+ compile-command: "make -C /export/bios/voyager2"
+ c-basic-offset: 8
+ End:
+*/
diff -x CVS -x SCCS -x BitKeeper -x ChangeSet -x *.o -x .*depend -x System.map -x
.version -x .config.old -x *.stamp -x *.flags -x *.ver -x *.rej -x *.orig -x *~ -x .#*
-urN freebios.orig/src/superio/NSC/pc97317/superio.c
freebios/src/superio/NSC/pc97317/superio.c
--- freebios.orig/src/superio/NSC/pc97317/superio.c Thu Jan 1 01:00:00 1970
+++ freebios/src/superio/NSC/pc97317/superio.c Fri Mar 15 08:56:36 2002
@@ -0,0 +1 @@
+
--
"Just how much can I get away with and still go to heaven?"
