Hello,
This patch handles the phy reset pin's polarity. AMD8111's PHY_RESET pin
is active high by default, but some PHY requires active low reset signal.
On mainboards which use 8111's PHY_RESET pin to reset PHY the bios
must select the correct PHY_RST_POL for 8111, otherwise the PHY chip
would always be held in reset state and can't be accessed by software.
I sent a similar patch several months ago but no response on this list,
would someone who has cvs commit right check and apply it?
--
Tao
diff -Naur freebios2-20050305-0000/src/include/device/pci_ids.h
freebios2-20050305-0000-lt/src/include/device/pci_ids.h
--- freebios2-20050305-0000/src/include/device/pci_ids.h 2004-12-11
04:50:43.000000000 +0800
+++ freebios2-20050305-0000-lt/src/include/device/pci_ids.h 2005-03-07
15:43:04.000000000 +0800
@@ -418,6 +418,7 @@
#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a
#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b
+#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462
#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463
#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450
#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451
diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c
--- freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c
2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/amd8111_nic.c
2005-03-18
16:17:04.000000000 +0800
@@ -8,18 +8,82 @@
#include <device/pci_ops.h>
#include "amd8111.h"
+#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val))
+#define CMD3 0x54
+
+typedef enum {
+ VAL3 = (1 << 31), /* VAL bit for byte 3 */
+ VAL2 = (1 << 23), /* VAL bit for byte 2 */
+ VAL1 = (1 << 15), /* VAL bit for byte 1 */
+ VAL0 = (1 << 7), /* VAL bit for byte 0 */
+}VAL_BITS;
+
+typedef enum {
+ /* VAL3 */
+ ASF_INIT_DONE_ALIAS = (1 << 29),
+ /* VAL2 */
+ JUMBO = (1 << 21),
+ VSIZE = (1 << 20),
+ VLONLY = (1 << 19),
+ VL_TAG_DEL = (1 << 18),
+ /* VAL1 */
+ EN_PMGR = (1 << 14),
+ INTLEVEL = (1 << 13),
+ FORCE_FULL_DUPLEX = (1 << 12),
+ FORCE_LINK_STATUS = (1 << 11),
+ APEP = (1 << 10),
+ MPPLBA = (1 << 9),
+ /* VAL0 */
+ RESET_PHY_PULSE = (1 << 2),
+ RESET_PHY = (1 << 1),
+ PHY_RST_POL = (1 << 0),
+}CMD3_BITS;
+
+static void nic_init(struct device *dev)
+{
+ struct southbridge_amd_amd8111_config *conf;
+ struct resource *resource;
+ void *mmio;
+
+ conf = dev->chip_info;
+ resource = find_resource(dev, PCI_BASE_ADDRESS_0);
+ mmio = (void *)resource->base;
+
+ /* Hard Reset PHY */
+ printk_debug("Reseting PHY... ");
+ if (conf->phy_lowreset) {
+ writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3);
+ } else {
+ writel(VAL0 | RESET_PHY, mmio + CMD3);
+ }
+ mdelay(15);
+ writel(RESET_PHY, mmio + CMD3);
+ printk_debug("Done\n");
+}
+
+static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ pci_write_config32(dev, 0xc8,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = lpci_set_subsystem,
+};
+
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = amd8111_enable,
- .init = 0,
+ .init = nic_init,
.scan_bus = 0,
+ .enable = amd8111_enable,
+ .ops_pci = &lops_pci,
};
static struct pci_driver nic_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7462,
+ .device = PCI_DEVICE_ID_AMD_8111_NIC,
};
diff -Naur freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h
freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h
--- freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h 2004-10-21
18:44:04.000000000 +0800
+++ freebios2-20050305-0000-lt/src/southbridge/amd/amd8111/chip.h
2005-03-07
16:12:27.000000000 +0800
@@ -5,6 +5,7 @@
{
unsigned int ide0_enable : 1;
unsigned int ide1_enable : 1;
+ unsigned int phy_lowreset : 1;
};
struct chip_operations;
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