Segher Boessenkool wrote: > >>It might be worth checking that there isn't a particular reason for > >>these. Just because posting writes are forbidden doesn't mean a > >>particular bridge won't screw it up... > > > >Well, I had already checked with Ben, who wrote the code, and my > >understanding is that the reads are intended to work around some > >misbehaving Apple bridges, > > None of the PCI interfaces on the U3 or U4 bridges have that > problem as far as I know. I think the workaround was copied > from code for older Apple bridges?
Okay, then the change should be fine for maple. > >but that a sync after the write (implied by > >releasing pci_lock in the generic pci code) should suffice for those. > > I don't see how a sync could help here at all, not more than > an eieio anyway? Alright, well, maybe take it up with Ben when I post the patch for powermac, since that's where it could actually matter. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
