The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.

Signed-off-by: Oliver O'Halloran <ooh...@gmail.com>
---
 arch/powerpc/include/asm/reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 7e50e47375d6..a3b6575c7842 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1303,7 +1303,7 @@ static inline void msr_check_and_clear(unsigned long bits)
                                "       .llong 0\n"                     \
                                ".previous"                             \
                        : "=r" (rval) \
-                       : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \
+                       : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
                        rval;})
 #else
 #define mftb()         ({unsigned long rval;   \
-- 
2.9.4

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