With the optimisations introduced by commit a46cc7a908 ("powerpc/mm/radix:
Improve TLB/PWC flushes"), flush_tlb_mm() no longer flushes the page walk
cache with radix. Switch to using flush_all_mm() to ensure the pwc and tlb
are properly flushed on the nmmu.Signed-off-by: Alistair Popple <alist...@popple.id.au> --- Michael, This depends on Frederic's series: http://patchwork.ozlabs.org/patch/809343/ http://patchwork.ozlabs.org/patch/809344/ Thanks. Alistair arch/powerpc/platforms/powernv/npu-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c index 2cb6cbe..2fff9a65 100644 --- a/arch/powerpc/platforms/powernv/npu-dma.c +++ b/arch/powerpc/platforms/powernv/npu-dma.c @@ -549,7 +549,7 @@ static void mmio_invalidate(struct npu_context *npu_context, int va, * Unfortunately the nest mmu does not support flushing specific * addresses so we have to flush the whole mm. */ - flush_tlb_mm(npu_context->mm); + flush_all_mm(npu_context->mm); /* * Loop over all the NPUs this process is active on and launch -- 2.1.4
