On Tue, 2018-10-16 at 20:58 +0300, Raz wrote: > Section 5.7.3 > "Storage accesses in real, hypervisor real, and virtual real > addressing modes are performed in a manner that depends on the > contents of MSR HV , VPM, VRMASD, HRMOR, RMLS, RMOR (see Chapter 2), > bit 0 of the > effective address (EA0)," > > Hello > 1. If MSR_IR = 0 and MSR_DR = 0, does it mean that addresses are not > translated by the MMU ?
It depends. If HV=1 (hypervisor mode), then they are only translated to the extent that HRMOR is applied if the MSB is 0, and untranslated if the MSB is 1. If HV=0 (guest mode), then they *are* translated but using a different mechanism than what's normally used when IR/DR=1. This mechanism depends on whether you are using the Radix or the Hash MMU, and the top 2 bits are ignored. With hash MMU, it's using things like VRMASD etc... (RMOR is deprecated afaik) to lookup a "Virtual real mode" area in the hash table. It's essentially a mapping of the guest "physical" space to real physical space. It's usually initialized (and maintained) by the HV but the guest can extend it using things like H_ENTER afaik. With the radix MMU, it's the guest physical space as mapped by the 2nd level page tables maintained by the hypervisor. > 2. If EA0 is the 63-rd bit of the effective address e address ? Does > this mean that the translation model is > derived from the address ? a non privileged context may access > privileged memory. Nope. Cheers, Ben.