On Tue, 2008-03-11 at 11:58 +0100, Laurent Pinchart wrote: > Hi everybody, > > is there any documentation describing interrupt handling for the powerpc > architecture ? I'm writing a driver for a cascaded interrupt controller and > the only source of information I found was the code.
I don't think there's much documentation. You might want to look at arch/powerpc/platforms/cell/axon_msi.c, it's a reasonably simple example of how to setup an irq_host and so on - well I think so :D > I'm particularly interested in information about irq hosts (allocation and > initialisation, especially the map and unmap callbacks) and irq chaining. > Different drivers seem to implement cascaded irqs differently (for instance > arch/powerpc/sysdev/uic.c uses setup_irq to register the cascaded irq > handler, while arch/powerpc/platforms/82xx/pq2ads-pci-pic.c uses > set_irq_chained_handler) so I'm a bit lost here. uic.c uses set_irq_chained_handler() now, so that probably answers that question. I don't think it makes all that much difference if you set it up by hand, but set_irq_chained_handler() is the neat way to do it. cheers -- Michael Ellerman OzLabs, IBM Australia Development Lab wwweb: http://michael.ellerman.id.au phone: +61 2 6212 1183 (tie line 70 21183) We do not inherit the earth from our ancestors, we borrow it from our children. - S.M.A.R.T Person
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