Hi, Christophe and everyone from the LinuxPPC community, Hope you are doing well! I was working with Daniel, and we were reviewing the ipic source code and came to these questions:
1. The first one came up while reviewing the document "Understanding IPIC" from NXP (*). The document states that: System Error Status Register (SERSR) - 0x40: Each bit in the SERSR register corresponds to a non-maskable error source that generates a machine check exception (MCP). These bits are cleared by writing the bit location with a logic 1. The interrupting source must be cleared before clearing the interrupts error status bit. System Error Mask Register (SERMR) - 0x44 When a machine check exception is signaled from one of the peripheral modules, its corresponding flag bit in this register is set. Any of the interrupting sources can be individually masked. We noticed that you changed the ipic_clear_mcp_status function by swapping SERMR to SERSR, but we don't fully understand why. Could you please elaborate on why this change is made? This because we had a code that was working before the patch and we would fully understand why it stopped working. From our perspective, both SERSR and SERMR are related to MCEs and honestly don't know what's the difference at the hardware level, and the role of every register on the machine check flow. It is also weird for us that before your patch the register SERSR wasn't used in any part of the Linux kernel. 2. In commit 8acb88682cc00a41a677c2455a7c992d you removed ipic_set_highest_priority(), ipic_enable_mcp() and ipic_disable_mcp()because it wasn't used but here we are confused because ipic_clear_mcp_status() sets all bits with the mask and in the old disable function the bits from the mask are cleared with a bitwise AND,changing the other bits from the SERMR register but the mcp_irq. ipic_clear: ipic_write<https://elixir.bootlin.com/linux/v4.1.13/ident/ipic_write>(primary_ipic<https://elixir.bootlin.com/linux/v4.1.13/ident/primary_ipic>->regs, IPIC_SERMR<https://elixir.bootlin.com/linux/v4.1.13/ident/IPIC_SERMR>, mask); ipic_disable: temp<https://elixir.bootlin.com/linux/v4.1.13/ident/temp> = ipic_read<https://elixir.bootlin.com/linux/v4.1.13/ident/ipic_read>(ipic<https://elixir.bootlin.com/linux/v4.1.13/ident/ipic>->regs, IPIC_SERMR<https://elixir.bootlin.com/linux/v4.1.13/ident/IPIC_SERMR>); temp<https://elixir.bootlin.com/linux/v4.1.13/ident/temp> &= (1 << (31 - mcp_irq)); ipic_write<https://elixir.bootlin.com/linux/v4.1.13/ident/ipic_write>(ipic<https://elixir.bootlin.com/linux/v4.1.13/ident/ipic>->regs, IPIC_SERMR<https://elixir.bootlin.com/linux/v4.1.13/ident/IPIC_SERMR>, temp<https://elixir.bootlin.com/linux/v4.1.13/ident/temp>); Isn't ipic_clear a set function instead of a clear function? This bring us confusion Another question is why these functions were created in the first place? 3. In the NXP document it states that: These bits are cleared by writing the bit location with a logic 1. The interrupting source must be cleared before clearing the interrupts error status bit. Does this mean that these registers work with negative logic? How is this managed in the kernel? The interrupting source is the SERMR register, the SERSR or any other? 4. What is the real difference between MCP and MCE? What are their uses? I know it is a lot of information but we are very confused about the use of these registers and we noticed that you are very involved on the PPC development. So we would like to hear from an expert. Thank you very much for your time, Pablo (*) https://www.nxp.com/docs/en/application-note/AN3797.pdf
