On 13/07/2019 01:28, Christoph Hellwig wrote:
On Fri, Jul 12, 2019 at 07:45:05PM +1000, Alexey Kardashevskiy wrote:
This is an attempt to allow DMA masks between 32..59 which are not large
enough to use either a PHB3 bypass mode or a sketchy bypass. Depending
on the max order, up to 40 is usually available.
Can you elaborate what you man with supported in detail? In the end
a DMA devices DMA capability is only really interesting as a lower
bound.
e.g. if you have a DMA that supports 40-bit DMA addressing we could
always treat it as if supports 32-bit addressing,and I thought the
powerpc code does that,
powerpc does that and this is what the patchset is changing as people
complained that 2GB DMA window has bad effects on AMD GPUs (cannot
allocate enough buffers) and 40/100Gbit devices (lower performance), I
do not have the details handy.
as the DMA API now relies on that.
Relies on what precisely? If a device cannot do full 64bit, then it has
to be no more than just 32bit?
Did I miss
something and it explicitly rejected that (in which case I didn't spot
the fix in this series), or is this just an optimization to handle these
devices more optimally, in which case maybe the changelog could be
improved a bit.
4/4 did this essentially:
- const u64 window_size = min((u64)pe->table_group.tce32_size,
max_memory);
+ const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
+ const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
where tce32_size==2<<30. The 4/4 commit log has the details, what is
missing there? Thanks,
--
Alexey
