And I forgot to Cc the DT maintainer/ML on this one :-/
On Wed, 3 Jun 2020 15:49:22 +0200
Boris Brezillon <boris.brezil...@collabora.com> wrote:
> Those properties are no longer parsed by the driver which is being passed
> those information by the core now. Let's deprecate them.
>
> Signed-off-by: Boris Brezillon <boris.brezil...@collabora.com>
> ---
> Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
> b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
> index fce4894f5a98..25f07c1f9e44 100644
> --- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt
> @@ -7,14 +7,16 @@ Required properties:
> - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
>
> Optional properties:
> -- fsl,upm-wait-flags : add chip-dependent short delays after running the
> - UPM pattern (0x1), after writing a data byte (0x2) or after
> - writing out a buffer (0x4).
> - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
> The corresponding address lines are used to select the chip.
> - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
> (R/B#). For multi-chip devices, "n" GPIO definitions are required
> according to the number of chips.
> +
> +Deprecated properties:
> +- fsl,upm-wait-flags : add chip-dependent short delays after running the
> + UPM pattern (0x1), after writing a data byte (0x2) or after
> + writing out a buffer (0x4).
> - chip-delay : chip dependent delay for transferring data from array to
> read registers (tR). Required if property "gpios" is not used
> (R/B# pins not connected).
> @@ -52,8 +54,6 @@ upm@3,0 {
> fsl,upm-cmd-offset = <0x08>;
> /* Multi-chip NAND device */
> fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
> - fsl,upm-wait-flags = <0x5>;
> - chip-delay = <25>; // in micro-seconds
>
> nand@0 {
> #address-cells = <1>;
