Hypervisor may choose not to enable Guest Translation Shootdown Enable (GTSE) option for the guest. When GTSE isn't ON, the guest OS isn't permitted to use instructions like tblie and tlbsync directly, but is expected to make hypervisor calls to get the TLB flushed.
This series enables the TLB flush routines in the radix code to off-load TLB flushing to hypervisor via the newly proposed hcall H_RPT_INVALIDATE. The specification of this hcall is still evolving while the patchset is posted here for any early comments. To easily check the availability of GTSE, it is made an MMU feature. (TODO: Check if this can be a static key instead of MMU feature) The OV5 handling and H_REGISTER_PROC_TBL hcall are changed to handle GTSE as an optionally available feature and to not assume GTSE when radix support is available. H_RPT_INVALIDATE ================ Syntax: int64 /* H_Success: Return code on successful completion */ /* H_Busy - repeat the call with the same */ /* H_P2, H_P3, H_P4, H_Parameter: Invalid parameters */ hcall(const uint64 H_RPT_INVALIDATE, /* Invalidate process scoped RPT lookaside information */ uint64 pid, /* PID to invalidate */ uint64 target, /* Invalidation target */ uint64 what, /* What type of lookaside information */ uint64 pages, /* Page sizes */ uint64 start, /* Start of Effective Address (EA) range */ uint64 end) /* End of EA range */ Invalidation targets (target) ----------------------------- Core MMU 0x01 /* All virtual processors in the partition */ Core local MMU 0x02 /* Current virtual processor */ Nest MMU 0x04 /* All nest/accelerator agents in use by the partition */ A combination of the above can be specified, except core and core local. What to invalidate (what) ------------------------- Reserved 0x0001 /* Reserved */ TLB 0x0002 /* Invalidate TLB */ PWC 0x0004 /* Invalidate Page Walk Cache */ PRS 0x0008 /* Invalidate Process Table Entries */ A combination of the above can be specified. Page size mask (pages) ---------------------- 4K 0x01 64K 0x02 2M 0x04 1G 0x08 All sizes (-1UL) A combination of the above can be specified. All page sizes can be selected with -1. Semantics: Invalidate radix tree lookaside information matching the parameters given. * Return H_P2, H_P3 or H_P4 if target, what or pages parameters are different from the defined values. * Return H_PARAMETER if (start, end) doesn't form a valid range. * May invalidate more translation information than was specified. * If start = 0 and end = -1, set the range to cover all valid addresses. Else start and end should be aligned to 4kB (lower 11 bits clear). * If pid = 0 then valid addresses are quadrant 3 and quadrant 0 spaces, Else valid addresses are quadrant 0. * Pages which are fully covered by the range are to be invalidated. Those which are partially covered are considered outside invalidation range, which allows a call to optimally invalidate ranges that may contain mixed page sizes. * Return H_SUCCESS on success. Bharata B Rao (3): powerpc/mm: Make GTSE as MMU FTR powerpc/prom_init: Ask for Radix GTSE only if supported. powerpc/pseries: H_REGISTER_PROC_TBL should ask for GTSE only if enabled Nicholas Piggin (1): powerpc/mm/book3s64/radix: Off-load TLB invalidations to host when !GTSE arch/powerpc/include/asm/hvcall.h | 1 + arch/powerpc/include/asm/mmu.h | 4 + arch/powerpc/include/asm/plpar_wrappers.h | 14 +++ arch/powerpc/kernel/dt_cpu_ftrs.c | 2 + arch/powerpc/kernel/prom_init.c | 13 +-- arch/powerpc/mm/book3s64/radix_tlb.c | 105 ++++++++++++++++++++-- arch/powerpc/mm/init_64.c | 6 +- arch/powerpc/platforms/pseries/lpar.c | 8 +- 8 files changed, 137 insertions(+), 16 deletions(-) -- 2.21.3