Make GTSE as an MMU feature and enable it by default for radix.
However for guest, conditionally enable it if hypervisor supports it
via OV5 vector.

Making GTSE as a MMU feature will make it easy to enable radix
without GTSE.

Signed-off-by: Bharata B Rao <bhar...@linux.ibm.com>
---
 arch/powerpc/include/asm/mmu.h    | 4 ++++
 arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
 arch/powerpc/mm/init_64.c         | 6 +++++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index f4ac25d4df05..884d51995934 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -28,6 +28,9 @@
  * Individual features below.
  */
 
+/* Guest Translation Shootdown Enable */
+#define MMU_FTR_GTSE                   ASM_CONST(0x00001000)
+
 /*
  * Support for 68 bit VA space. We added that from ISA 2.05
  */
@@ -173,6 +176,7 @@ enum {
 #endif
 #ifdef CONFIG_PPC_RADIX_MMU
                MMU_FTR_TYPE_RADIX |
+               MMU_FTR_GTSE |
 #ifdef CONFIG_PPC_KUAP
                MMU_FTR_RADIX_KUAP |
 #endif /* CONFIG_PPC_KUAP */
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c 
b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 3a409517c031..571aa39e35d5 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -337,6 +337,8 @@ static int __init feat_enable_mmu_radix(struct 
dt_cpu_feature *f)
 #ifdef CONFIG_PPC_RADIX_MMU
        cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
        cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
+       /* TODO: Does this need a separate cpu dt feature? */
+       cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
        cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
 
        return 1;
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index c7ce4ec5060e..feb9bed9177c 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -408,13 +408,17 @@ static void __init early_check_vec5(void)
                if (!(vec5[OV5_INDX(OV5_RADIX_GTSE)] &
                                                OV5_FEAT(OV5_RADIX_GTSE))) {
                        pr_warn("WARNING: Hypervisor doesn't support RADIX with 
GTSE\n");
-               }
+                       cur_cpu_spec->mmu_features &= ~MMU_FTR_GTSE;
+               } else
+                       cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
                /* Do radix anyway - the hypervisor said we had to */
                cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
        } else if (mmu_supported == OV5_FEAT(OV5_MMU_HASH)) {
                /* Hypervisor only supports hash - disable radix */
                cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;
+               cur_cpu_spec->mmu_features &= ~MMU_FTR_GTSE;
        }
+
 }
 
 void __init mmu_early_init_devtree(void)
-- 
2.21.3

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