Nicholas Piggin <npig...@gmail.com> writes: > LPCR[HDICE]=0 suppresses hypervisor decrementer exceptions on some > processors, so it must be enabled before HDEC is set. > > Rather than set it in the host LPCR then setting HDEC, move the HDEC > update to after the guest MMU context (including LPCR) is loaded. > There shouldn't be much concern with delaying HDEC by some 10s or 100s > of nanoseconds by setting it a bit later. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com> > --- > arch/powerpc/kvm/book3s_hv.c | 19 +++++++------------ > 1 file changed, 7 insertions(+), 12 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 1f2ba8955c6a..ffde1917ab68 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -3505,20 +3505,9 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu > *vcpu, u64 time_limit, > host_dawrx1 = mfspr(SPRN_DAWRX1); > } > > - /* > - * P8 and P9 suppress the HDEC exception when LPCR[HDICE] = 0, > - * so set HDICE before writing HDEC. > - */ > - mtspr(SPRN_LPCR, kvm->arch.host_lpcr | LPCR_HDICE); > - isync(); > - > hdec = time_limit - mftb(); > - if (hdec < 0) { > - mtspr(SPRN_LPCR, kvm->arch.host_lpcr); > - isync(); > + if (hdec < 0) > return BOOK3S_INTERRUPT_HV_DECREMENTER; > - } > - mtspr(SPRN_HDEC, hdec); > > if (vc->tb_offset) { > u64 new_tb = mftb() + vc->tb_offset; > @@ -3564,6 +3553,12 @@ static int kvmhv_load_hv_regs_and_go(struct kvm_vcpu > *vcpu, u64 time_limit, > > switch_mmu_to_guest_radix(kvm, vcpu, lpcr); > > + /* > + * P9 suppresses the HDEC exception when LPCR[HDICE] = 0, > + * so set guest LPCR (with HDICE) before writing HDEC. > + */ > + mtspr(SPRN_HDEC, hdec); > + > mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0); > mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);