On Thu, 12 Jun 2008 16:24:13 +0200 Stefan Roese <[EMAIL PROTECTED]> wrote:
> On Wednesday 11 June 2008, Josh Boyer wrote: > > The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine > > this by looking for a zero value in the PCI cache line size register. > > However, some drivers write to this register upon initialization. This can > > cause MRMs to be used on these chips, which may cause deadlocks on PLB4. > > > > The workaround implemented here introduces a new indirect_type flag, called > > PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure > > in the pci fixup function for 4xx PCI bridges by determining if the bridge > > is compatible with 440EPx/GRx. The flag is checked in the > > indirect_write_config function, and forces any writes to the > > PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these > > chips. > > > > A similar workaround has been tested by AMCC on various PCI cards, such as > > the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with > > the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. > > With the workaround in place, the card functioned properly and only Memory > > Reads were seen on the bus with the analyzer. > > > > Signed-off-by: Josh Boyer <[EMAIL PROTECTED]> > > Acked-by: Stefan Roese <[EMAIL PROTECTED]> > > I manually applied your patch (since it doesn't apply clean as discussed on > IRC) and tested it on my Sequoia with a modified PCI USB driver changing > PCI_CACHE_LINE_SIZE. Thanks. I blame git for being dumb. I guess I'll have to switch to using git-format-patch instead of quilt. In the meantime, I'll queue this up for .27. josh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev