Interrupt vectors were not being populated for all architected
interrupt types, which could lead to crashes rather than a message for
unhandled interrupts.
0x20 sized vectors require some reworking of the code to fit. This
also adds support for HV / HSRR type interrupts which will be used in
a later change.
Acked-by: Thomas Huth <th...@redhat.com>
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
Since v3:
- Build fix [Joel]
lib/powerpc/asm/ppc_asm.h | 3 ++
powerpc/cstart64.S | 79 ++++++++++++++++++++++++++++++++-------
2 files changed, 68 insertions(+), 14 deletions(-)
diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h
index 6299ff53..46b4be00 100644
--- a/lib/powerpc/asm/ppc_asm.h
+++ b/lib/powerpc/asm/ppc_asm.h
@@ -35,6 +35,9 @@
#endif /* __BYTE_ORDER__ */
+#define SPR_HSRR0 0x13A
+#define SPR_HSRR1 0x13B
+
/* Machine State Register definitions: */
#define MSR_EE_BIT 15 /* External Interrupts Enable */
#define MSR_SF_BIT 63 /* 64-bit mode */
diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S
index 34e39341..b7514100 100644
--- a/powerpc/cstart64.S
+++ b/powerpc/cstart64.S
@@ -184,14 +184,6 @@ call_handler:
mfcr r0
std r0,_CCR(r1)
- /* nip and msr */
-
- mfsrr0 r0
- std r0, _NIP(r1)
-
- mfsrr1 r0
- std r0, _MSR(r1)
-
/* restore TOC pointer */
LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR)
@@ -238,6 +230,7 @@ call_handler:
.section .text.ex
+/* [H]VECTOR must not be more than 8 instructions to fit in 0x20 vectors */
.macro VECTOR vec
. = \vec
@@ -246,19 +239,28 @@ call_handler:
subi r1,r1, INT_FRAME_SIZE
/* save r0 and ctr to call generic handler */
-
SAVE_GPR(0,r1)
- mfctr r0
- std r0,_CTR(r1)
+ li r0,\vec
+ std r0,_TRAP(r1)
- ld r0, P_HANDLER(0)
- mtctr r0
+ b handler_trampoline
+.endm
+
+.macro HVECTOR vec
+ . = \vec
+
+ mtsprg1 r1 /* save r1 */
+ mfsprg0 r1 /* get exception stack address */
+ subi r1,r1, INT_FRAME_SIZE
+
+ /* save r0 and ctr to call generic handler */
+ SAVE_GPR(0,r1)
li r0,\vec
std r0,_TRAP(r1)
- bctr
+ b handler_htrampoline
.endm
. = 0x100
@@ -268,12 +270,61 @@ __start_interrupts:
VECTOR(0x100)
VECTOR(0x200)
VECTOR(0x300)
+VECTOR(0x380)
VECTOR(0x400)
+VECTOR(0x480)
VECTOR(0x500)
VECTOR(0x600)
VECTOR(0x700)
VECTOR(0x800)
VECTOR(0x900)
+HVECTOR(0x980)
+VECTOR(0xa00)
+VECTOR(0xc00)
+VECTOR(0xd00)
+HVECTOR(0xe00)
+HVECTOR(0xe20)
+HVECTOR(0xe40)
+HVECTOR(0xe60)
+HVECTOR(0xe80)
+HVECTOR(0xea0)
+VECTOR(0xf00)
+VECTOR(0xf20)
+VECTOR(0xf40)
+VECTOR(0xf60)
+HVECTOR(0xf80)
+
+handler_trampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfsrr0 r0
+ std r0, _NIP(r1)
+
+ mfsrr1 r0
+ std r0, _MSR(r1)
+
+ bctr
+
+handler_htrampoline:
+ mfctr r0
+ std r0,_CTR(r1)
+
+ ld r0, P_HANDLER(0)
+ mtctr r0
+
+ /* nip and msr */
+ mfspr r0, SPR_HSRR0
+ std r0, _NIP(r1)
+
+ mfspr r0, SPR_HSRR1
+ std r0, _MSR(r1)
+
+ bctr
.align 7
.globl __end_interrupts
--
2.40.1
