On Thu, Feb 15, 2024 at 10:31:58AM +0000, Ryan Roberts wrote: > Split __flush_tlb_range() into __flush_tlb_range_nosync() + > __flush_tlb_range(), in the same way as the existing flush_tlb_page() > arrangement. This allows calling __flush_tlb_range_nosync() to elide the > trailing DSB. Forthcoming "contpte" code will take advantage of this > when clearing the young bit from a contiguous range of ptes. > > Ordering between dsb and mmu_notifier_arch_invalidate_secondary_tlbs() > has changed, but now aligns with the ordering of __flush_tlb_page(). It > has been discussed that __flush_tlb_page() may be wrong though. > Regardless, both will be resolved separately if needed. > > Reviewed-by: David Hildenbrand <da...@redhat.com> > Tested-by: John Hubbard <jhubb...@nvidia.com> > Signed-off-by: Ryan Roberts <ryan.robe...@arm.com>
Acked-by: Catalin Marinas <catalin.mari...@arm.com>
