> On Thu, Mar 26, 2026 at 02:29:05PM +0800, Wei Fang wrote: > > Add bindings for NETC switch. This switch is a PCIe function of NETC > > IP, it supports advanced QoS with 8 traffic classes and 4 drop > > resilience levels, and a full range of TSN standards capabilities. > > The switch CPU > > Nit: double space before TSN.
Thanks for catching this, I will fix it. > > > port connects to an internal ENETC port, which is also a PCIe function > > of NETC IP. So these two ports use a light-weight "pseudo MAC" instead > > of a back-to-back MAC, because the "pseudo MAC" provides the > > delineation between switch and ENETC, this translates to lower power > > (less logic and > > what's means "this translates", do you means "this help reduce power and > latency." This sentence is excerpted from the NETC Block Guide. It is equivalent to "it means". > > > memory) and lower delay (as there is no serialization delay across > > this link). > > > > Signed-off-by: Wei Fang <[email protected]> > > --- > > .../bindings/net/dsa/nxp,netc-switch.yaml | 130 ++++++++++++++++++ > > 1 file changed, 130 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml > > b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml > > new file mode 100644 > > index 000000000000..e34a4e3504c3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml > > @@ -0,0 +1,130 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/nxp,netc-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NETC Switch family > > + > > +description: > > Nit use ">" for multi paragraph. Okay, I suppose I also need to add '>' to the below description of "dsa,member" property. > > others look good > > Reviewed-by: Frank Li <[email protected]> > > > + The NETC presents itself as a multi-function PCIe Root Complex > > + Integrated Endpoint (RCiEP) and provides full 802.1Q Ethernet > > + switch functionality, advanced QoS with 8 traffic classes and 4 > > + drop resilience levels, and a full range of TSN standards capabilities. > > + > > + The CPU port of the switch connects to an internal ENETC. The > > + switch and the internal ENETC are fully integrated into the NETC > > + IP, a back-to-back MAC is not required. Instead, a light-weight > > + "pseudo MAC" provides the delineation between the switch and ENETC. > > + This translates to lower power (less logic and memory) and lower > > + delay (as there is no serialization delay across this link). > > + > > +maintainers: > > + - Wei Fang <[email protected]> > > + > > +properties: > > + compatible: > > + enum: > > + - pci1131,eef2 > > + > > + reg: > > + maxItems: 1 > > + > > + dsa,member: > > + description: > > + The property indicates DSA cluster and switch index. For NETC switch, > > + the valid range of the switch index is 1 ~ 7, the index is reflected > > + in the switch tag as an indication of the switch ID where the frame > > + originated. The value 0 is reserved for ENETC VEPA switch, whose ID > > + is hardwired to zero. > > + > > +$ref: dsa.yaml# > > + > > +patternProperties: > > + "^(ethernet-)?ports$": > > + type: object > > + additionalProperties: true > > + patternProperties: > > + "^(ethernet-)?port@[0-9a-f]$": > > + type: object > > + > > + $ref: dsa-port.yaml# > > + > > + properties: > > + clocks: > > + items: > > + - description: MAC transmit/receive reference clock. > > + > > + clock-names: > > + items: > > + - const: ref > > + > > + mdio: > > + $ref: /schemas/net/mdio.yaml# > > + unevaluatedProperties: false > > + description: > > + Optional child node for switch port, otherwise use NETC > EMDIO. > > + > > + unevaluatedProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - dsa,member > > + > > +allOf: > > + - $ref: /schemas/pci/pci-device.yaml > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + pcie { > > + #address-cells = <3>; > > + #size-cells = <2>; > > + > > + ethernet-switch@0,2 { > > + compatible = "pci1131,eef2"; > > + reg = <0x200 0 0 0 0>; > > + dsa,member = <0 1>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_switch>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + phy-handle = <ðphy0>; > > + phy-mode = "mii"; > > + }; > > + > > + port@1 { > > + reg = <1>; > > + phy-handle = <ðphy1>; > > + phy-mode = "mii"; > > + }; > > + > > + port@2 { > > + reg = <2>; > > + clocks = <&scmi_clk 103>; > > + clock-names = "ref"; > > + phy-handle = <ðphy2>; > > + phy-mode = "rgmii-id"; > > + }; > > + > > + port@3 { > > + reg = <3>; > > + ethernet = <&enetc3>; > > + phy-mode = "internal"; > > + > > + fixed-link { > > + speed = <2500>; > > + full-duplex; > > + pause; > > + }; > > + }; > > + }; > > + }; > > + }; > > -- > > 2.34.1 > >
