The buffer pool is a quantity of memory available for buffering a group of flows (e.g. frames having the same priority, frames received from the same port), while waiting to be transmitted on a port. The buffer pool tracks internal memory consumption with upper bound limits and optionally a non-shared portion when associated with a shared buffer pool. Currently the shared buffer pool is not supported, it will be added in the future.
For i.MX94, the switch has 4 ports and 8 buffer pools, so each port is allocated two buffer pools. For frames with priorities of 0 to 3, they will be mapped to the first buffer pool; For frames with priorities of 4 to 7, they will be mapped to the second buffer pool. Each buffer pool has a flow control on threshold and a flow control off threshold. By setting these threshold, add the flow control support to each port. Signed-off-by: Wei Fang <[email protected]> --- drivers/net/dsa/netc/netc_main.c | 163 ++++++++++++++++++++++++++ drivers/net/dsa/netc/netc_switch.h | 9 ++ drivers/net/dsa/netc/netc_switch_hw.h | 13 ++ 3 files changed, 185 insertions(+) diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c index 3609d83ac363..62611263a93f 100644 --- a/drivers/net/dsa/netc/netc_main.c +++ b/drivers/net/dsa/netc/netc_main.c @@ -379,6 +379,8 @@ static void netc_port_set_mlo(struct netc_port *np, enum netc_mlo mlo) static void netc_port_fixed_config(struct netc_port *np) { + u32 pqnt = 0xffff, qth = 0xff00; + /* Default IPV and DR setting */ netc_port_rmw(np, NETC_PQOSMR, PQOSMR_VS | PQOSMR_VE, PQOSMR_VS | PQOSMR_VE); @@ -386,6 +388,15 @@ static void netc_port_fixed_config(struct netc_port *np) /* Enable L2 and L3 DOS */ netc_port_rmw(np, NETC_PCR, PCR_L2DOSE | PCR_L3DOSE, PCR_L2DOSE | PCR_L3DOSE); + + /* Set the quanta value of TX PAUSE frame */ + netc_mac_port_wr(np, NETC_PM_PAUSE_QUANTA(0), pqnt); + + /* When a quanta timer counts down and reaches this value, + * the MAC sends a refresh PAUSE frame with the programmed + * full quanta value if a pause condition still exists. + */ + netc_mac_port_wr(np, NETC_PM_PAUSE_TRHESH(0), qth); } static void netc_port_default_config(struct netc_port *np) @@ -617,6 +628,117 @@ static int netc_add_standalone_fdb_bcast_entry(struct netc_switch *priv) bcast, NETC_STANDALONE_PVID); } +static u32 netc_get_buffer_pool_num(struct netc_switch *priv) +{ + return netc_base_rd(&priv->regs, NETC_BPCAPR) & BPCAPR_NUM_BP; +} + +static void netc_port_set_pbpmcr(struct netc_port *np, u64 mapping) +{ + u32 pbpmcr0 = lower_32_bits(mapping); + u32 pbpmcr1 = upper_32_bits(mapping); + + netc_port_wr(np, NETC_PBPMCR0, pbpmcr0); + netc_port_wr(np, NETC_PBPMCR1, pbpmcr1); +} + +static void netc_ipv_to_buffer_pool_mapping(struct netc_switch *priv) +{ + int bp_per_port = priv->num_bp / priv->info->num_ports; + int q, r, num, i, ipv; + u32 bp_id; + + if (!bp_per_port) { + q = priv->info->num_ports / priv->num_bp; + r = priv->info->num_ports % priv->num_bp; + num = (q + 1) * r; + + /* Multiple ports share a buffer pool, the mapping relationship + * between ports and buffer pools is as follows: + * + * - For the first 'r' buffer pools, each buffer pool is shared + * by 'q + 1' ports. + * - After that, each buffer pool is share by 'q' ports. + * - All IPVs of a port are mapped to the same buffer pool. + */ + for (i = 0; i < priv->info->num_ports; i++) { + u64 mapping = 0; + + if (i < num) + bp_id = i / (q + 1); + else + bp_id = r + (i - num) / q; + + for (ipv = 0; ipv < NETC_IPV_NUM; ipv++) + mapping |= (u64)bp_id << (ipv * 8); + + netc_port_set_pbpmcr(priv->ports[i], mapping); + } + + return; + } + + q = NETC_IPV_NUM / bp_per_port; + r = NETC_IPV_NUM % bp_per_port; + num = q + r; + + /* IPV-to–buffer-pool mapping per port: + * Each port is allocated 'bp_per_port' buffer pools and supports 8 + * IPVs, where a higher IPV indicates a higher frame priority. Each + * IPV can be mapped to only one buffer pool. + * + * The mapping rule is as follows: + * - The first 'num' IPVs share the port's first buffer pool (index + * 'base_id'). + * - After that, every 'q' IPVs share one buffer pool, with pool + * indices increasing sequentially. + */ + for (i = 0; i < priv->info->num_ports; i++) { + u32 base_id = i * bp_per_port; + u64 mapping = 0; + + bp_id = base_id; + + for (ipv = 0; ipv < NETC_IPV_NUM; ipv++) { + /* Update the buffer pool index */ + if (ipv >= num) + bp_id = base_id + ((ipv - num) / q) + 1; + + mapping |= (u64)bp_id << (ipv * 8); + } + + netc_port_set_pbpmcr(priv->ports[i], mapping); + } +} + +static int netc_switch_bpt_default_config(struct netc_switch *priv) +{ + /* priv->num_bp is read from register, its value is hardcoded as + * a non-zero value. + */ + priv->num_bp = netc_get_buffer_pool_num(priv); + priv->bpt_list = devm_kcalloc(priv->dev, priv->num_bp, + sizeof(struct bpt_cfge_data), + GFP_KERNEL); + if (!priv->bpt_list) + return -ENOMEM; + + /* Initialize the maximum threshold of each buffer pool entry */ + for (int i = 0; i < priv->num_bp; i++) { + struct bpt_cfge_data *cfge = &priv->bpt_list[i]; + int err; + + cfge->max_thresh = cpu_to_le16(NETC_BP_THRESH); + err = ntmp_bpt_update_entry(&priv->ntmp, i, cfge); + if (err) + return err; + } + + netc_ipv_to_buffer_pool_mapping(priv); + + return 0; +} + static int netc_setup(struct dsa_switch *ds) { struct netc_switch *priv = ds->priv; @@ -644,6 +766,10 @@ static int netc_setup(struct dsa_switch *ds) dsa_switch_for_each_available_port(dp, ds) netc_port_default_config(priv->ports[dp->index]); + err = netc_switch_bpt_default_config(priv); + if (err) + goto free_lock_and_ntmp_user; + err = netc_add_standalone_vlan_entry(priv); if (err) goto free_lock_and_ntmp_user; @@ -1195,6 +1321,41 @@ static void netc_port_set_rmii_mii_mac(struct netc_port *np, netc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val); } +static void netc_port_set_tx_pause(struct netc_port *np, bool tx_pause) +{ + struct netc_switch *priv = np->switch_priv; + int port = np->dp->index; + int i, j, num_bp; + + num_bp = priv->num_bp / priv->info->num_ports; + for (i = 0, j = port * num_bp; i < num_bp; i++, j++) { + struct bpt_cfge_data *cfge = &priv->bpt_list[j]; + struct bpt_cfge_data old_cfge = *cfge; + + if (tx_pause) { + cfge->fc_on_thresh = cpu_to_le16(NETC_FC_THRESH_ON); + cfge->fc_off_thresh = cpu_to_le16(NETC_FC_THRESH_OFF); + cfge->fccfg_sbpen = FIELD_PREP(BPT_FC_CFG, + BPT_FC_CFG_EN_BPFC); + cfge->fc_ports = cpu_to_le32(BIT(port)); + } else { + cfge->fc_on_thresh = cpu_to_le16(0); + cfge->fc_off_thresh = cpu_to_le16(0); + cfge->fccfg_sbpen = 0; + cfge->fc_ports = cpu_to_le32(0); + } + + if (ntmp_bpt_update_entry(&priv->ntmp, j, cfge)) + *cfge = old_cfge; + } +} + +static void netc_port_set_rx_pause(struct netc_port *np, bool rx_pause) +{ + netc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_PAUSE_IGN, + rx_pause ? 0 : PM_CMD_CFG_PAUSE_IGN); +} + static void netc_port_mac_rx_enable(struct netc_port *np) { netc_port_rmw(np, NETC_POR, PCR_RXDIS, 0); @@ -1256,6 +1417,8 @@ static void netc_mac_link_up(struct phylink_config *config, interface == PHY_INTERFACE_MODE_MII) netc_port_set_rmii_mii_mac(np, speed, duplex); + netc_port_set_tx_pause(np, tx_pause); + netc_port_set_rx_pause(np, rx_pause); netc_port_mac_rx_enable(np); } diff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h index 4b229a71578e..7ebffb136b2f 100644 --- a/drivers/net/dsa/netc/netc_switch.h +++ b/drivers/net/dsa/netc/netc_switch.h @@ -32,6 +32,12 @@ #define NETC_STANDALONE_PVID 0 +#define NETC_IPV_NUM 8 +/* MANT = bits 11:4, EXP = bits 3:0, threshold = MANT * 2 ^ EXP */ +#define NETC_BP_THRESH 0x334 +#define NETC_FC_THRESH_ON 0x533 +#define NETC_FC_THRESH_OFF 0x3c3 + struct netc_switch; struct netc_switch_info { @@ -90,6 +96,9 @@ struct netc_switch { struct ntmp_user ntmp; struct hlist_head fdb_list; struct mutex fdbt_lock; /* FDB table lock */ + + u32 num_bp; + struct bpt_cfge_data *bpt_list; }; #define NETC_PRIV(ds) ((struct netc_switch *)((ds)->priv)) diff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h index c6a0c0a8ff8a..1e1c0d279a21 100644 --- a/drivers/net/dsa/netc/netc_switch_hw.h +++ b/drivers/net/dsa/netc/netc_switch_hw.h @@ -12,6 +12,12 @@ #define NETC_SWITCH_DEVICE_ID 0xeef2 /* Definition of Switch base registers */ +#define NETC_BPCAPR 0x0008 +#define BPCAPR_NUM_BP GENMASK(7, 0) + +#define NETC_PBPMCR0 0x0400 +#define NETC_PBPMCR1 0x0404 + #define NETC_CBDRMR(a) (0x0800 + (a) * 0x30) #define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30) #define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30) @@ -138,6 +144,7 @@ enum netc_stg_stage { #define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400) #define PM_CMD_CFG_TX_EN BIT(0) #define PM_CMD_CFG_RX_EN BIT(1) +#define PM_CMD_CFG_PAUSE_IGN BIT(8) #define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400) #define PM_MAXFRAM GENMASK(15, 0) @@ -145,6 +152,12 @@ enum netc_stg_stage { #define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400) #define PM_IEVENT_RX_EMPTY BIT(6) +#define NETC_PM_PAUSE_QUANTA(a) (0x1054 + (a) * 0x400) +#define PAUSE_QUANTA_PQNT GENMASK(15, 0) + +#define NETC_PM_PAUSE_TRHESH(a) (0x1064 + (a) * 0x400) +#define PAUSE_TRHESH_QTH GENMASK(15, 0) + #define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400) #define PM_IF_MODE_IFMODE GENMASK(2, 0) #define IFMODE_MII 1 -- 2.34.1
