On 6/8/26 09:41, Jörg Rödel wrote:
> From: Melody Wang <[email protected]>
>
> The #HV IPI NAE event allows the guest to send an IPI to other vCPUs in the
> guest when the Restricted Injection feature is enabled. Implement the NAE
> event as per GHCB specification.
>
> Co-developed-by: Thomas Lendacky <[email protected]>
> Signed-off-by: Thomas Lendacky <[email protected]>
> Signed-off-by: Melody Wang <[email protected]>
> Signed-off-by: Joerg Roedel <[email protected]>
This patch should come before the patch #6 where restricted injection is
enabled.
> ---
> arch/x86/include/uapi/asm/svm.h | 1 +
> arch/x86/kvm/lapic.c | 24 +++++++++++++++++++++++-
> arch/x86/kvm/lapic.h | 2 ++
> arch/x86/kvm/svm/sev.c | 28 ++++++++++++++++++++++++++++
> 4 files changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h
> index d84a13ac4627..d281dd21c540 100644
> --- a/arch/x86/include/uapi/asm/svm.h
> +++ b/arch/x86/include/uapi/asm/svm.h
> @@ -122,6 +122,7 @@
> #define SVM_VMGEXIT_HVDB_SET 1
> #define SVM_VMGEXIT_HVDB_QUERY 2
> #define SVM_VMGEXIT_HVDB_CLEAR 3
> +#define SVM_VMGEXIT_HV_IPI 0x80000015ull
Looks like spaces instead of tabs between the name and the value.
Thanks,
Tom
> #define SVM_VMGEXIT_SNP_RUN_VMPL 0x80000018ull
> #define SVM_VMGEXIT_SAVIC 0x8000001aull
> #define SVM_VMGEXIT_SAVIC_REGISTER_GPA 0
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 4078e624ca66..ab40a2e4ab9d 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2558,7 +2558,7 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic,
> u32 reg, u32 val)
> static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
> gpa_t address, int len, const void *data)
> {
> - struct kvm_lapic *apic = to_lapic(this);
> + struct kvm_lapic *apic = this ? to_lapic(this) : vcpu->arch.apic;
> unsigned int offset = address - apic->base_address;
> u32 val;
>
> @@ -3583,3 +3583,25 @@ void kvm_lapic_exit(void)
> static_key_deferred_flush(&apic_sw_disabled);
> WARN_ON(static_branch_unlikely(&apic_sw_disabled.key));
> }
> +
> +/* Send IPI by writing ICR with MSR write when X2APIC enabled, with mmio
> write when XAPIC enabled */
> +int kvm_xapic_x2apic_send_ipi(struct kvm_vcpu *vcpu, u64 data)
> +{
> + u32 icr_msr_addr = APIC_BASE_MSR + (APIC_ICR >> 4);
> + struct kvm_lapic *apic = vcpu->arch.apic;
> + gpa_t gpa = apic->base_address + APIC_ICR;
> +
> + if (!kvm_lapic_enabled(vcpu))
> + return 1;
> +
> + if (vcpu->arch.apic_base & X2APIC_ENABLE) {
> + if (!kvm_x2apic_msr_write(vcpu, icr_msr_addr, data))
> + return 0;
> + } else {
> + if (!apic_mmio_write(vcpu, NULL, gpa, 4, &data))
> + return 0;
> + }
> +
> + return 1;
> +}
> +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_xapic_x2apic_send_ipi);
> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
> index 274885af4ebc..afd440c88981 100644
> --- a/arch/x86/kvm/lapic.h
> +++ b/arch/x86/kvm/lapic.h
> @@ -156,6 +156,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr,
> u64 *data);
> int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
> void kvm_lapic_exit(void);
>
> +int kvm_xapic_x2apic_send_ipi(struct kvm_vcpu *vcpu, u64 data);
> +
> u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
>
> static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
> index 369fb1e36f58..d04f71836ef7 100644
> --- a/arch/x86/kvm/svm/sev.c
> +++ b/arch/x86/kvm/svm/sev.c
> @@ -35,6 +35,7 @@
> #include "svm_ops.h"
> #include "cpuid.h"
> #include "trace.h"
> +#include "lapic.h"
>
> #define GHCB_VERSION_MAX 2ULL
> #define GHCB_VERSION_MIN 1ULL
> @@ -3538,6 +3539,10 @@ static int sev_es_validate_vmgexit(struct vcpu_svm
> *svm)
> if (!is_sev_snp_guest(vcpu))
> goto vmgexit_err;
> break;
> + case SVM_VMGEXIT_HV_IPI:
> + if (!sev_snp_guest(vcpu->kvm))
> + goto vmgexit_err;
> + break;
> default:
> reason = GHCB_ERR_INVALID_EVENT;
> goto vmgexit_err;
> @@ -4416,6 +4421,22 @@ static int sev_snp_hv_doorbell_page(struct vcpu_svm
> *svm)
> return 0;
> }
>
> +static int sev_snp_hv_ipi(struct vcpu_svm *svm)
> +{
> + struct kvm_vcpu *vcpu = &svm->vcpu;
> + u64 icr_info;
> +
> + if (!sev_snp_guest(vcpu->kvm))
> + return -EINVAL;
> +
> + icr_info = svm->vmcb->control.exit_info_1;
> +
> + if (kvm_xapic_x2apic_send_ipi(vcpu, icr_info))
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm)
> {
> struct vmcb_control_area *control = &svm->vmcb->control;
> @@ -4698,6 +4719,13 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu)
> ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
> GHCB_ERR_INVALID_INPUT);
> }
>
> + ret = 1;
> + break;
> + case SVM_VMGEXIT_HV_IPI:
> + if (sev_snp_hv_ipi(svm)) {
> + ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 2);
> + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
> GHCB_ERR_INVALID_INPUT);
> + }
> ret = 1;
> break;
> case SVM_VMGEXIT_UNSUPPORTED_EVENT:
