Benjamin Herrenschmidt wrote:
On Fri, 2008-10-24 at 16:18 -0700, David Miller wrote:
From: Kumar Gala <[EMAIL PROTECTED]>
Date: Fri, 24 Oct 2008 10:57:38 -0500
Commit 18404756765c713a0be4eb1082920c04822ce588 introduced a regression
on a subset of SMP based PPC systems whose interrupt controller only
allow setting an irq to a single processor. The previous behavior
was only CPU0 was initially setup to get interrupts. Revert back
to that behavior.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
I really don't remember getting all of my interrupts only on cpu 0
on sparc64 before any of these changes. I therefore find all of
this quite mysterious. :-)
Well, I don't know how you do it but on powerpc, we explicitely fill the
affinity masks at boot time when we can spread interrupts... Maybe we
should change it the other way around and limit the mask when we can't ?
It's hard to tell for sure at this stage.
Ben.
What does this all mean to my GigE (dual 1.1 GHz 7455s)? Is this
thing supposed to be able to spread irq between its cpus?
kevin
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