On Mar 20, 2009, at 12:48 AM, Benjamin Herrenschmidt wrote:
On Wed, 2009-03-11 at 10:18 -0500, Kumar Gala wrote:
CoreInt provides a mechansim to deliver the IRQ vector directly
into the core on an interrupt (via the SPR EPR) rather than having
to go IACK on the PIC. This is suppose to provide an improvment
in interrupt latency by reducing the time to get the IRQ vector.
Signed-off-by: Kumar Gala <ga...@kernel.crashing.org>
---
* Fixed MPIC_GREG_GCONF_COREINT flag to be 0x60000000 as per spec
and pointed about by Dave
Are you sure ? That's 2 bits ...
Yeah. We expanded the mode field to two bits (mask would be 0x60000000)
0x00 = pass through (interrupts routed to IRQ0)
0x01 = Mixed mode
0x10 = reserved
0x11 = External proxy / coreint
- k
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