Joakim Tjernlund wrote:
I am a bit confused, what isn't worth it?
Enabling cacheing on MURAM, at least when used for buffer descriptors. The cache line ping-pong would probably outweigh the cost of the uncached accesses.
Currently MURAM isn't used by ucc_geth,
Hmm. I looked in the driver and saw numerous muram allocations, but I didn't try to follow the driver enough to ensure that they were for the ring. I'd assumed it was similar to the CPM1/CPM2 driver.
3) as gianfar, dma_alloc_coherent(). I presume this is uncacheable memory?
It would be uncacheable on systems without coherent DMA, but I don't think there are any such systems that use gianfar.
My guess would be 2 or 3. Do they have the same synchronization sematics?
No, unfortunately. PowerPC sync instructions are a bit complicated. For example, you can use eieio to sync between reading the interrupt status register and checking the ring buffer, if they're both mapped I+G, but not if the former is I+G and the latter is cacheable (you need a full sync in that case).
-Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
