On Tue, May 12, 2009 at 8:36 PM, David Gibson <da...@gibson.dropbear.id.au> wrote: > On Tue, May 12, 2009 at 05:10:46PM -0700, Stephen Neuendorffer wrote: >> >> Another possibility is to pad the DTB with a DESYNC command and the >> correct pad frame, just in case it cannot be prevented. > > Um.. one thing I'm missing in this discussion of attaching the dtb to > the bitstream: I don't see how the bitstream becomes accessible to > the kernel at runtime. Unless you were exposing the dtb as part of > the fpga programming, but I thought you explicitly weren't doing that > because of limited bram space. > > I imagine this is simply due to my ignorance about FPGA techniques, > but if someone could enlighten me...?
In this case the processor has access to the flash where the FPGA bitstreams are stored and a set of registers in a CPLD which tells it which bitstream was used to configure the FPGA. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
