On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote: > Dear David Jander, > > In message <[email protected]> you wrote: > > Complete workaround for DTLB errata in e300c2/c3/c4 processors. > > > > Due to the bug, the hardware-implemented LRU algorythm always goes to way > > 1 of the TLB. This fix implements the proposed software workaround in > > form of a LRW table for chosing the TLB-way. > > > > Signed-off-by: Kumar Gala <[email protected]> > > Signed-off-by: David Jander <[email protected]> > > What is the actual status of this patch? > > Patchwork (http://patchwork.ozlabs.org/patch/24502/) says it's > "superseded" - but by what? > > I can't see such code in mainline - what happened to it?
I can see the code in mainline ... but only in the -data- TLB miss handler, not the instruction one... Kumar ? Shouldn't we have the workaround in both ? Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
