On Thu, Jul 2, 2009 at 1:57 PM, Grant Likely<[email protected]> wrote: > From: Grant Likely <[email protected]> > > When doing register reads, it is possible for there to be a stale > data ready bit set which will cause subsequent reads to return > prematurely with incorrect data. This patch fixes the issues by > ensuring stale data is cleared before starting another transaction. > > Signed-off-by: Grant Likely <[email protected]>
Acked-by: Jon Smirl <[email protected]> > --- > > sound/soc/fsl/mpc5200_psc_ac97.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > > diff --git a/sound/soc/fsl/mpc5200_psc_ac97.c > b/sound/soc/fsl/mpc5200_psc_ac97.c > index 794a247..9b8503f 100644 > --- a/sound/soc/fsl/mpc5200_psc_ac97.c > +++ b/sound/soc/fsl/mpc5200_psc_ac97.c > @@ -41,6 +41,10 @@ static unsigned short psc_ac97_read(struct snd_ac97 *ac97, > unsigned short reg) > pr_err("timeout on ac97 bus (rdy)\n"); > return -ENODEV; > } > + > + /* Force clear the data valid bit */ > + in_be32(&psc_dma->psc_regs->ac97_data); > + > /* Send the read */ > out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24)); > > > -- Jon Smirl [email protected] _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
