On Thu, 2009-08-06 at 14:57 +1000, Paul Mackerras wrote: > This provides a mechanism to allow the perf_counters code to access > user memory in a PMU interrupt routine. Such an access can cause > various kinds of interrupt: SLB miss, MMU hash table miss, segment > table miss, or TLB miss, depending on the processor. This commit > only deals with the classic/server processors that use an MMU hash > table, not processors that have software-loaded TLBs.
.../... > Signed-off-by: Paul Mackerras <[email protected]> Acked-by: Benjamin Herrenschmidt <[email protected]> As discussed in the lab, you should also do a pre-req patch to pgtable.h that changes ppc32 with 64-bit PTE without CONFIG_SMP to use the same path as SMP to order the stores to the two halves of the PTEs though. Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
