On Fri, 2009-09-25 at 10:31 +0200, Joakim Tjernlund wrote: > > The main problem with 8xx it does not update the DAR register in > the TLB Miss/Fault handlers for cache instructions :( It on old bug > that was found only some years ago. > > I think the old comment is correct though, as I recall it was Marcelo > that found the problem and added the workaround.
But the TLB needs flushing on more than just the cache instructions, no ? IE. We take a TLB miss, there's no valid PTE, we put one of those "unpopulated" entries in and get into the page fault, at which point we do a set_pte, we -still- need to do an invalidation to get rid of the unpopulated entry so it gets a new TLB miss no ? Without that, it's just going to fault over and over again... In any case, I think flushing unconditionally the target address isn't going to hurt since we are just changing its PTE anyways. As for the DAR problem, I'm not sure whether we really need a workaround since I haven't seem much people complaining about it so far :-) Can you educate me more on the problem ? Can it be fixed without bloating those handlers to oblivion ? Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
