> > Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote on 06/10/2009 > 08:45:47: > > > > On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote: > > > > > Yes, I would too but TLB Miss knows nothing about load/store, protection > > > etc. > > > because DSISR isn't set. So I cannot see any other way than the TLB Error > > > way. > > > > Hrm... that MMU really sucks more than I thought :-( > > > > I'll go read the manual and think about that a bit more. > > I realise now that for an ITLB Miss I can work out everything I need. > an ITLB must be a read en everything else is in the linux pte. > Just check present and user, add accessed if not already there. > I blame that on too little sleep :)
bugger, more bugs I think. Need to fix the TLB code some more _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
