Adds binding documentation for cache sram for the PQ3 and some QorIQ based platforms.
Signed-off-by: Vivek Mahajan <[email protected]> --- .../powerpc/dts-bindings/fsl/85xx_cache_sram.txt | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/fsl/85xx_cache_sram.txt diff --git a/Documentation/powerpc/dts-bindings/fsl/85xx_cache_sram.txt b/Documentation/powerpc/dts-bindings/fsl/85xx_cache_sram.txt new file mode 100644 index 0000000..781955f --- /dev/null +++ b/Documentation/powerpc/dts-bindings/fsl/85xx_cache_sram.txt @@ -0,0 +1,20 @@ +* Freescale PQ3 and QorIQ based Cache SRAM + +Freescale's mpc85xx and some QorIQ platforms provide an +option of configuring a part of (or full) cache memory +as SRAM. This cache SRAM representation in the device +tree should be done as under:- + +Required properties: + +- compatible : should be "fsl,p2020-cache-sram" +- fsl,cache-sram-ctlr-handle : points to the L2 controller +- reg : offset and length of the cache-sram. + +Example: + +cache-s...@fff00000 { + fsl,cache-sram-ctlr-handle = <&L2>; + reg = <0 0xfff00000 0 0x10000>; + compatible = "fsl,p2020-cache-sram"; +}; -- 1.5.6.5 _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
