"Albrecht Dreß" <albrecht.dr...@arcor.de> wrote on 2010/02/18 10:09:23: > > Hi Joakim: > > > Does this reset sequence also send a START condition for every clock? > > Please see the attached scan from a scope output, showing the first two out of > the 9 sequences at 375 kHz (that's what the 5200's divider makes from 400 kHz > requested). Resolution is 2us/div and 1V/div for both signals. The waveform > itself for each of the 9 sequences is exactly the same we had before with the > old solution, just the timing is faster and adjusted to the ii2c clock, i.e. > the /relative/ waveforms look identical for slower clocks. > > Any insight if this is *really* correct would be great, as I'm not an i2c > expert. I can only say it reliably fixes the bus hangs I saw!
Looks like you do a STOP then START each time SCL is high so yes you do a START each SCL and a STOP too. Don't think the STOP will hurt though. Timing is OK for FAST-MODE(400kHz), cannot say for STANDARD-MODE though need a 100Khz scope img for that. The times to look for are: tHD;STA, tSU;STA, tSU;STO and tBUF at least that is what I have identified. Jocke _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
