> The problem cropped up when there was a lot of traffic to the NAND
> (Samsung K9WAGU08U1B-PIB0), with the NAND being on the LBC along with
> a video chip that needed constant and prompt attention.
>
> What I would see is that, as the writes happened, the erases would
> wind up batched and issued all at once, such that frequently 400-700
> erases were issued in rapid succession with a 1ms LBC BUSY cycle per
> erase.
Are those just the reads of the status register polling to
determine when the sector erase has completed ?
In which case a software delay beteen the reads might work.
Writes probably also have to be polled, but the individual
writes happen faster.
It is possible that an uncached read of another memory area
will stall the cpu long enough to allow another LBC master in.
One every few writes might be enough.
I had to do something similar on rather different hardware ...
David
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