Scott Wood <scottw...@freescale.com> wrote on 2010/12/13 18:33:56: > > On Mon, 13 Dec 2010 11:32:00 +0100 > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote: > > > "David Laight" <david.lai...@aculab.com> wrote on 2010/12/13 09:33:37: > > > > > > > > > > > An external IRQ line would let you limit interrupts to rising edges > > > > > rather than all edges, though you'd lose the ability to > > > > > directly read the line status. > > > > > > > > oh, one cannot read the IRQ line? didn't know that. > > > > Also I not sure all Freescale CPUs can do rising edge. > > Ah right, 83xx has IPIC rather than MPIC. > > > > I suspect that you may be able to leave the interupt masked, but still > > > read the 'interrupt pending' register. Which would have the same effect. > > > > Ah, that should work too. I should be able to read the 'interrupt pending' > > register at all times, even when it isn't masked. > > This could work OK if you have board logic to invert the signal.
yeah, just a NAND gate :) > > > What if one has several NAND chips to build a big FS? Is the NAND > > controller equipped to handle that? > > FCM can drive one NAND chip per eLBC chipselect, though possibly you > could go beyond that with a board-logic chipselect mechanism. hmm, then I guess one would have to use one GPIO/IRQ per NAND chip? _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
