> Subject: RapidIO: multiple mport support for QorIQ > > I'm planning to add support for the multiple(2) mports supported by the > Freescale > p2020 processor. I'm currently looking at the fsl layer to add in support for > multiple port enumeration, and work up from there. It looks like the upper > layers already have at least partial support for this. My question is, are > there > any efforts already ongoing I can hop in on so as not to duplicate effort? > If not, > I'll just do it. >
I'm not aware of someone working on that. > There is some divergance in respect to the memory map that is non-trivial that > I'm not sure how to handle, since it totally hoses the common fsl_rio.c > structures. > I think I want to create a new set that's p2020 specific, but has potential > to be > shared with the other QorIQ series, so dumping the pseries-specific code into > platforms/pseries seems like a reasonable way to go. Thoughts? The dual-port RIO is very common on QorIQ chips. I won't suggest you add P2020 specific memory map file. The two port memory map should also be compatible with one port driver. -Leo _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
