Hello list,
A whole bunch of dts file such a p2020ds.dts, p2020rdb.dts and probably
lots of other variants as well (haven't checked the manuals of the
others). Claim their i2c controller to be 'fsl-i2c'
If you then look in i2c/busses/i2c.mpc.c this will end up calling
mpc_i2c_setup_8xxx() in fsl_i2c_probe() with a prescale value of 0 which
goes to mpc_i2c_get_fdr_8xxx() here prescale gets set to one and the
divider value gets calculated.
The problem is that the P2020 datasheet mentions: "The serial bit clock
frequency of SCL is equal to one half the platform (CCB) clock divided
by the designated divider. Note that the frequency divider value can be
changed at any point in a program." Implying that the factor two is not
taken into account. For this to function correctly the prescale value
should be set to a value two.
Which could be solved by adding another mpc_i2c_data for this type or by
using the mpc_i2c_data_8543 which also has a prescaler value of two. Or
to define an alternative structure for the p2020 alike system. However
at this point I don't know how this varies between the different px0x0
systems since I have only a p2020 at my disposal. So I would appreciate
it if somebody with a broader view on this SoCs can up with a usable
solution.
This issue will only propagate if the dts sets the clock-frequency field
for the i2c controller in question is set.
gr
E.
--
Elie De Brauwer
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