Hello. On 28-03-2011 22:28, tma...@apm.com wrote:
From: Tirumala Marri <tma...@apm.com>
Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode.
Signed-off-by: Tirumala R Marri <tma...@apm.com> Signed-off-by: Fushen Chen <fc...@apm.com> Signed-off-by: Mark Miesfeld <mmiesf...@apm.com>
This patch should precede patch 9 as patch 9 uses config. options defined here.
diff --git a/drivers/usb/otg/dwc/Kconfig b/drivers/usb/otg/dwc/Kconfig new file mode 100644 index 0000000..a8f22cb --- /dev/null +++ b/drivers/usb/otg/dwc/Kconfig @@ -0,0 +1,88 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +#
[...]
+# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG && (DWC_DEVICE_ONLY || USB_DWC_OTG)
Haven't we just defined this in patch 9? Redefinition of options isn't correct.
+config DWC_OTG_REG_LE + bool "DWC Little Endian Register"
This should preferrably be passed via the platform data, I think.
+ depends on USB_DWC_OTG + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + bool "DWC FIFO Little Endian"
This too.
+ depends on USB_DWC_OTG + default n
"default n" not needed.
+ help + OTG core FIFO access is Little-Endian.
Little endian registers and big endian FIFO by default?
+ +config DWC_LIMITED_XFER_SIZE + bool "DWC Endpoint Limited Xfer Size" + depends on USB_GADGET_DWC_HDRC + default n
Not needed.
+ help + Bit fields in the Device EP Transfer Size Register is 11 bits.
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