On Jun 23, 2011, at 2:24 AM, Aggrwal Poonam-B10812 wrote: > > >> -----Original Message----- >> From: linuxppc-dev-bounces+poonam.aggrwal=freescale....@lists.ozlabs.org >> [mailto:linuxppc-dev- >> bounces+poonam.aggrwal=freescale....@lists.ozlabs.org] On Behalf Of Kumar >> Gala >> Sent: Wednesday, June 22, 2011 5:04 PM >> To: Kushwaha Prabhakar-B32579 >> Cc: meet2pra...@gmail.com; devicetree-disc...@lists.ozlabs.org; linuxppc- >> d...@lists.ozlabs.org >> Subject: Re: [PATCH] powerpc/85xx:DTS: Fix tbi node location for Px020RDB >> >> >> On Jun 7, 2011, at 9:49 PM, Prabhakar Kushwaha wrote: >> >>> ten-bit interface (TBI) module is part of SoC not board. >>> >>> Move tbi entries from board related dts files to Si dts. >>> >>> Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com> >>> --- >>> Based upon >> http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch >> next) >>> >>> arch/powerpc/boot/dts/p1020rdb.dts | 9 --------- >>> arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 8 -------- >>> arch/powerpc/boot/dts/p1020si.dtsi | 6 +++++- >>> arch/powerpc/boot/dts/p2020rdb.dts | 8 -------- >>> arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 8 -------- >>> arch/powerpc/boot/dts/p2020si.dtsi | 6 +++++- >>> 6 files changed, 10 insertions(+), 35 deletions(-) >>> >>> diff --git a/arch/powerpc/boot/dts/p1020rdb.dts >> b/arch/powerpc/boot/dts/p1020rdb.dts >>> index d6a8ae4..a4e5d6c 100644 >>> --- a/arch/powerpc/boot/dts/p1020rdb.dts >>> +++ b/arch/powerpc/boot/dts/p1020rdb.dts >>> @@ -211,14 +211,6 @@ >>> }; >>> }; >>> >>> - mdio@25000 { >>> - >>> - tbi0: tbi-phy@11 { >>> - reg = <0x11>; >>> - device_type = "tbi-phy"; >>> - }; >>> - }; >>> - >>> enet0: ethernet@b0000 { >>> fixed-link = <1 1 1000 0 0>; >>> phy-connection-type = "rgmii-id"; >>> @@ -227,7 +219,6 @@ >>> >>> enet1: ethernet@b1000 { >>> phy-handle = <&phy0>; >>> - tbi-handle = <&tbi0>; >>> phy-connection-type = "sgmii"; >>> >>> }; >> >> I'm not sure we should do this. The phy address we pick is board >> specific so it should NOT be in .dtsi > The TBI phy and it's address is internal to SOC.
But it is configured to NOT conflict with external PHY addresses. This the setting is board specific in my opinion. - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
