On Mon, Apr 30, 2012 at 07:58:33AM -0300, Mauro Carvalho Chehab wrote: > It seems you have a very short memory.
Oh, puh-lease, let's don't start with the insults now. You're not a saint yourself. And maybe the fact that I'm having hard time grasping your code is maybe because it is a load of crap and you seem to generate a lot of senseless drivel when explaining what it does. And don't get me started on the patch bombs. So, let's stay constructive here before I, as the last and only one person reviewing this stinking pile stops messing with it (I got other stuff to do, you know) and NACK it completely. > For example, this is the mapping used by the second memory controller of the > SB machine > I'm using on my tests: > > [52803.640043] EDAC DEBUG: sbridge_probe: Registering MC#1 (2 of 2) > ... > [52803.640062] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc(): allocating 7196 > bytes for mci data (12 dimms, 12 csrows/channels) > [52803.640070] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: initializing 12 dimms > [52803.640072] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 0: dimm0 (0:0:0): > row 0, chan 0 > [52803.640074] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 1: dimm1 (0:1:0): > row 0, chan 1 > [52803.640077] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 2: dimm2 (0:2:0): > row 0, chan 2 > [52803.640080] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 3: dimm3 (1:0:0): > row 0, chan 3 > [52803.640083] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 4: dimm4 (1:1:0): > row 1, chan 0 > [52803.640086] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 5: dimm5 (1:2:0): > row 1, chan 1 > [52803.640089] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 6: dimm6 (2:0:0): > row 1, chan 2 > [52803.640092] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 7: dimm7 (2:1:0): > row 1, chan 3 > [52803.640095] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 8: dimm8 (2:2:0): > row 2, chan 0 > [52803.640098] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 9: dimm9 (3:0:0): > row 2, chan 1 > [52803.640101] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 10: dimm10 (3:1:0): > row 2, chan 2 > [52803.640104] EDAC DEBUG: edac_mc_alloc: edac_mc_alloc: 11: dimm11 (3:2:0): > row 2, chan 3 > > With the above info, it is clear that the DIMM located at mc#1, channel#3 > slot#2 is > called "dimm11" at the new API, and corresponds to "csrow 2, channel 3" for a > legacy > EDAC API call. Are all those DIMM slots above populated? What happens if they're not, are you issuing the same dimm0-dimm11 lines for slots which aren't even populated? I have a much better idea: Generally, this debug info should come from the specific driver that allocates the dimm descriptors, not from the EDAC core. This way, you know in the driver which slots are populated and those which are not should be omitted. This way it says "initializing 12 dimms" and the user thinks there are 12 DIMMs on his system where this might not be true. -- Regards/Gruss, Boris. Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach GM: Alberto Bozzo Reg: Dornach, Landkreis Muenchen HRB Nr. 43632 WEEE Registernr: 129 19551 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev