> -----Original Message----- > From: Wood Scott-B07421 > Sent: Tuesday, June 19, 2012 12:47 AM > To: Sethi Varun-B16395 > Cc: Kumar Gala; Wood Scott-B07421; Linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error interrupt support. > > On 06/18/2012 02:12 PM, Sethi Varun-B16395 wrote: > > > > > >>>> +/* > >>>>> + * Error interrupt registers > >>>>> + */ > >>>>> + > >>>>> +#define MPIC_ERR_INT_BASE 0x3900 > >>>>> +#define MPIC_ERR_INT_EISR 0x0000 > >>>>> +#define MPIC_ERR_INT_EIMR 0x0010 > >>>>> + > >>>>> #define MPIC_MAX_IRQ_SOURCES 2048 > >>>>> #define MPIC_MAX_CPUS 32 > >>>>> #define MPIC_MAX_ISU 32 > >>>>> > >>>>> #define MPIC_MAX_TIMER 8 > >>>>> #define MPIC_MAX_IPI 4 > >>>>> +#define MPIC_MAX_ERR 32 > >>>> > >>>> Should probably be 64 > >>> > >>> This patch supports MPIC 4.1 and EISR0. When support is added for > >>> EISR1 (didn't realize this was coming until your comment prompted me > >>> to check...), this should be updated, but this change alone would > >>> not make it work. > >> > >> Would prefer we handle this now rather than later (T4240 is going to > >> need > >> EISR1 support). > > Hi Kumar, > > As of now I don't have a proper mechanism to test this functionality. > > I will submit a follow up patch for EISR1/EIMR1 support once I have a > > mechanism to test this functionality. > > You could still write the code in a way that scales to multiple EISRs, > and test that it works with EISR0. > Yes, but I would like to submit the patch once I have tested it.
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