On Tue, 2013-07-09 at 16:03 +0800, Tiejun Chen wrote: > book3e have no real MMU mode so we have to create a 1:1 TLB > mapping to make sure we can access the real physical address. > And correct something to support this pseudo real mode on book3e. > > Signed-off-by: Tiejun Chen <tiejun.c...@windriver.com>
Why do we need to be able to directly access physical addresses? > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S > index f1a7ce7..20cbb98 100644 > --- a/arch/powerpc/kernel/misc_64.S > +++ b/arch/powerpc/kernel/misc_64.S > @@ -460,6 +460,49 @@ kexec_flag: > > > #ifdef CONFIG_KEXEC > +#ifdef CONFIG_PPC_BOOK3E > +/* BOOK3E have no a real MMU mode so we have to setup the initial TLB > + * for a core to map v:0 to p:0 as 1:1. This current implementation > + * assume that 1G is enough for kexec. > + */ > +#include <asm/mmu.h> #includes go at the top of the file. > +kexec_create_tlb: > + /* Invalidate all TLBs to avoid any TLB conflict. */ > + PPC_TLBILX_ALL(0,R0) > + sync > + isync > + > + mfspr r10,SPRN_TLB1CFG > + andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */ > + subi r10,r10,1 /* Often its always safe to use last */ > + lis r9,MAS0_TLBSEL(1)@h > + rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */ Hardcoding TLB1 makes this FSL-specific code, but you've put it in a non-FSL-specific place. > +/* Setup a temp mapping v:0 to p:0 as 1:1 and return to it. > + */ > +#ifdef CONFIG_SMP > +#define M_IF_SMP MAS2_M > +#else > +#define M_IF_SMP 0 > +#endif > + mtspr SPRN_MAS0,r9 > + > + lis r9,(MAS1_VALID|MAS1_IPROT)@h > + ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l > + mtspr SPRN_MAS1,r9 What if the machine has less than 1 GiB of RAM? We could get speculative accesses to non-present addresses. Though it looks like the normal 64-bit init sequence has the same problem... -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
